Hardened event counters for anomaly detection
View Patent ↗A collection of techniques allow for the detection of covert malware that attempts to hide its existence on a system by leveraging both trusted hardware event counters and the particular memory addresses (as well as the sequences of such addresses) of the instructions that are generating the suspected malicious activity. By monitoring the address distribution's specific patterns over time, one can build a behavioral model (i.e., “fingerprint”) of a particular process—and later attempt to match suspected malicious processes to the stored behavioral models. Whenever the actual measured behavior of a suspected malicious process fails to match said stored behavioral models, the system or system administrator may attempt to perform rehabilitative actions on the computer system to locate and remove the malware hiding on the system.
1. A non-transitory computer readable medium with instructions stored thereon, the instructions comprising instructions that, when executed, cause a computer system to:
monitor a first set of hardware counters of the computer system over a first time period, thereby producing first fingerprint data for each of one or more operating system processes, wherein the first fingerprint data for each of the one or more operating system processes comprises a phase space graph for one or more of the first set of hardware counters, and wherein each phase space graph comprises a plurality of uni-directional transitions between memory addresses associated with one or more of the first set of hardware counters;
monitor the first set of hardware counters of the computer system over a second time period in a secure environment not controlled by an operating system of the computer system, thereby producing first runtime data for each of one or more operating system processes;
compare the first runtime data for each of the one or more operating system processes with the first fingerprint data for the corresponding operating system process; and
indicate whether the first runtime data for any of the one or more operating system processes differs by a predetermined threshold from the first fingerprint data for the corresponding operating system process.
2. The non-transitory computer readable medium of claim 1 , wherein the instructions that, when executed, cause the computer system to monitor a first set of hardware counters of the computer system over a first time period comprise instructions that, when executed, cause the computer system to:
monitor memory addresses corresponding to the first set of hardware counters during the first time period.
3. The non-transitory computer readable medium of claim 2 , wherein the instructions that, when executed, cause the computer system to monitor the first set of hardware counters of the computer system over a second time period comprise instructions that, when executed, cause the computer system to:
monitor memory addresses corresponding to the first set of hardware counters during the second time period.
4. The non-transitory computer readable medium of claim 1 , wherein the first set of hardware counters comprises a hardware counter corresponding to at least one of the following events: machine clear, cache miss, branch miss, self-modifying code, debugging event, single step event, store forward miss, misaligned memory reference, Instruction Translation Lookaside Buffer (ITLB) flush, Translation Lookaside Buffer (TLB) miss, indirect call, conditional branch, trap, context switch, power management event, and explicit stack pointer change instruction.
5. The non-transitory computer readable medium of claim 1 , wherein the instructions that, when executed, cause the computer system to monitor a first set of hardware counters of the computer system over a first time period further comprise instructions that, when executed, cause the computer system to:
monitor relative memory addresses corresponding to the first set of hardware counters during the first time period, wherein the relative memory addresses are computed from a base load position of a process in memory.
6. The non-transitory computer readable medium of claim 1 , wherein the instructions that, when executed, cause the computer system to monitor a first set of hardware counters of the computer system over a first time period comprise instructions that, when executed, further cause the computer system to:
monitor the first set of hardware counters of a second computer system over the first time period;
combine the monitored first set of hardware counters of the second computer system with the monitored first set of hardware counters of the computer system; and
produce first fingerprint data for each of one or more operating system processes using the combined monitored first set of hardware counters of the second computer system and the monitored first set of hardware counters of the computer system.
7. The non-transitory computer readable medium of claim 1 , wherein the instructions that, when executed, cause the computer system to monitor a first set of hardware counters of the computer system over a first time period comprise instructions that, when executed, cause the computer system to:
monitor a number of transitions of memory addresses corresponding to at least one of the first set of hardware counters during the first time period.
8. The non-transitory computer readable medium of claim 1 , wherein the first fingerprint data is monitored from a controlled test environment.
9. The non-transitory computer readable medium of claim 1 , wherein at least one of the hardware counters in the first set of hardware counters comprises a hardware counter that may not be reset.
10. A method of detecting anomalies, comprising:
monitoring a first set of hardware counters of a computer system over a first time period, thereby producing first fingerprint data for each of one or more operating system processes, wherein the first fingerprint data for each of the one or more operating system processes comprises a phase space graph for one or more of the first set of hardware counters, and wherein each phase space graph comprises a plurality of uni-directional transitions between memory addresses associated with one or more of the first set of hardware counters;
monitoring the first set of hardware counters of the computer system over a second time period in a secure environment not controlled by an operating system of the computer system, thereby producing first runtime data for each of one or more operating system processes;
comparing the first runtime data for each of the one or more operating system processes with the first fingerprint data for the corresponding operating system process; and
indicating whether the first runtime data for any of the one or more operating system processes differs by a predetermined threshold from the first fingerprint data for the corresponding operating system process.
11. The method of claim 10 , wherein monitoring a first set of hardware counters of the computer system over a first time period comprises:
monitoring memory addresses corresponding to the first set of hardware counters during the first time period.
12. The method of claim 11 , wherein monitoring a first set of hardware counters of the computer system over a second time period comprises:
monitoring memory addresses corresponding to the first set of hardware counters during the second time period.
13. The method of claim 10 , wherein the first set of hardware counters comprises a hardware counter corresponding to at least one of the following events: machine clear, cache miss, branch miss, self-modifying code, debugging event, single step event, store forward miss, misaligned memory reference, Instruction Translation Lookaside Buffer (ITLB) flush, Translation Lookaside Buffer (TLB) miss, indirect call, conditional branch, trap, context switch, power management event, and explicit stack pointer change instruction.
14. The method of claim 10 , wherein monitoring a first set of hardware counters of the computer system over a first time period comprises:
monitoring relative memory addresses corresponding to the first set of hardware counters during the first time period, wherein the relative memory addresses are computed from a base load position of a process in memory.
15. The method of claim 10 , wherein monitoring a first set of hardware counters of the computer system over a first time period further comprises:
monitoring the first set of hardware counters of a second computer system over the first time period;
combining the monitored first set of hardware counters of the second computer system with the monitored first set of hardware counters of the computer system; and
producing first fingerprint data for each of one or more operating system processes using the combined monitored first set of hardware counters of the second computer system and the monitored first set of hardware counters of the computer system.
16. The method of claim 10 , wherein monitoring a first set of hardware counters of the computer system over a first time period comprises:
monitoring a number of transitions of memory addresses corresponding to at least one of the first set of hardware counters during the first time period.
17. The method of claim 10 , wherein the first fingerprint data is monitored from a controlled test environment.
18. The method of claim 10 , wherein monitoring a first set of hardware counters of the computer system over a second time period comprises:
monitoring a number of transitions of memory addresses corresponding to at least one of the first set of hardware counters during the second time period.
19. The method of claim 18 , wherein the number of transitions monitored is based, at least in part, on a type of event that is associated with the at least one of the first set of hardware counters.
20. A computer system, comprising:
a hardware processor;
an operating system, comprising instructions that when executed by the processor control the processor and provide an operating system environment for other software to execute on the processor;
an anomaly detection software, comprising instructions that, when executed by the processor, cause the processor to:
monitor a first set of hardware counters of the computer system over a first time period, thereby producing first fingerprint data for each of one or more operating system processes, wherein the first fingerprint data for each of the one or more operating system processes comprises a phase space graph for one or more of the first set of hardware counters, and wherein each phase space graph comprises a plurality of uni-directional transitions between memory addresses associated with one or more of the first set of hardware counters;
monitor the first set of hardware counters of the computer system over a second time period in a secure environment not controlled by the operating system of the computer system, thereby producing first runtime data for each of one or more operating system processes;
compare the first runtime data for each of the one or more operating system processes with the first fingerprint data for the corresponding operating system process; and
indicate whether the first runtime data for any of the one or more operating system processes differs by a predetermined threshold from with the first fingerprint data for the corresponding operating system process.
21. The computer system of claim 20 , wherein the instructions that, when executed, cause the processor to monitor a first set of hardware counters of the computer system over a first time period comprise instructions that, when executed, cause the processor to:
monitor a number of transitions of memory addresses corresponding to at least one of the first set of hardware counters during the first time period.
22. The computer system of claim 20 , wherein the first fingerprint data is monitored from a controlled test environment.
23. The computer system of claim 20 , wherein the instructions that, when executed, cause the processor to monitor a first set of hardware counters of the computer system over a second time period comprise instructions that, when executed, cause the processor to:
monitor a number of transitions of memory addresses corresponding to at least one of the first set of hardware counters during the second time period.
24. The computer system of claim 23 , wherein the number of transitions monitored is based, at least in part, on a type of event that is associated with the at least one of the first set of hardware counters.
25. The computer system of claim 20 , wherein the instructions that, when executed, cause the processor to monitor a first set of hardware counters of the computer system over a first time period comprise instructions that, when executed, cause the processor to:
monitor relative memory addresses corresponding to the first set of hardware counters during the first time period, wherein the relative memory addresses are computed from a base load position of a process in memory.