Granted Patent B2

US 9,563,222 · App. 14/708,017 · Granted Feb 7, 2017

Abstract

Claims (57)

1. A reference signal distribution system, comprising:

a first subsystem biased by a reference current and configured to establish a differential voltage between a first node and a second node; and

a second subsystem driven by the differential voltage and configured to generate a copy current associated with the reference current, the second subsystem comprising:

a first transistor, including:

a first end;

a second end; and

a control end connected to the first node; and

a second transistor, including:

a first end;

a second end connected to the second end of the first transistor; and

a control end connected to the second node.

2. The reference signal distribution system of claim 1 , wherein the first subsystem comprises:

a third transistor, including:

a first end coupled to the first node;

a second end; and

a control end coupled to the first end of the third transistor; and

a fourth transistor, including:

a first end coupled to the second node;

a second end connected to the second end of the third transistor; and

a control end coupled to the first end of the fourth transistor.

3. The reference signal distribution system of claim 2 , wherein a ratio between the copy current and the reference current is associated with a ratio between a size of the first transistor and a size of the third transistor, and associated with a ratio between a size of the second transistor and a size of the fourth transistor.

4. The reference signal distribution system of claim 2 , wherein:

the first transistor and the third transistor are transistors of a first doping type; and

the second transistor and the fourth transistor are transistors of a second doping type different from the first doping type.

5. The reference signal distribution system of claim 2 , wherein the second subsystem further comprises:

a fifth transistor, including:

a first end configured to receive the copy current;

a second end coupled to the first end of the first transistor; and

a control end coupled to a third node; and

a sixth transistor, including:

a first end;

a second end coupled to the first end of the second transistor; and

a control end coupled to a fourth node.

6. The reference signal distribution system of claim 5 , wherein the first subsystem further comprises:

a first cascode bias coupled between the first node and the third node; and

a second cascode bias coupled between the second node and the fourth node.

7. The reference signal distribution system of claim 5 , wherein:

the first transistor, the third transistor, and the fifth transistor are transistors of a first doping type; and

the second transistor, the fourth transistor, and the sixth transistor are transistors of a second doping type different from the first doping type.

8. The reference signal distribution system of claim 1 , wherein:

the first subsystem further comprises:

a voltage source configured to supply a reference voltage; and

a first resister coupled in series to the voltage source to convert the reference voltage into the reference current; and

the second subsystem further comprises:

a second resister configured to convert the copy current into a copy voltage, wherein the copy voltage is associated with the reference voltage.

9. A method of distributing reference signals, comprising:

providing a reference current in a first subsystem that includes a first floating complimentary metal-oxide-semiconductor (CMOS) series transistor pair coupled between a first node and a second node;

biasing the first floating CMOS series transistor pair by the reference current to establish a differential voltage between the first node and the second node;

coupling a second floating CMOS series transistor pair of a second subsystem to the first node and the second node to receive the differential voltage; and

generating a copy current associated with the reference current at the second subsystem using the second floating CMOS series transistor pair driven by the differential voltage.

10. The method of claim 9 , further comprising:

providing a reference voltage at the first subsystem;

converting the reference voltage into the reference current at the first subsystem;

converting the copy current into a copy voltage at the first subsystem, wherein the copy voltage is associated with the reference voltage.

11. The method of claim 9 , further comprising:

coupling a first end of the second floating CMOS series transistor pair to a power supply via a first current buffer at the second subsystem; and

coupling a second end of the second floating CMOS series transistor pair to a power offset via a second current buffer at the second subsystem.

Assignments (9)