Method for manufacturing semiconductor device
To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.
1. A method for manufacturing a semiconductor device, comprising the steps of:
(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,
wherein a first electrode pad group and a second electrode pad group are arranged over the second surface of the second semiconductor chip,
wherein the first electrode pad group includes a plurality of first electrode pads arranged in a matrix of n rows and m columns (n<m),
wherein n is greater than 1;
wherein the second electrode pad group includes a plurality of second electrode pads,
wherein a plurality of projection electrodes is arranged over the first surface of the first semiconductor chip,
the (a) step including the steps of:
(a1) recognizing the second electrode pad group as a recognition mark;
(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and
(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling with the plurality of first electrode pads of the second semiconductor hip and the projection electrodes of the first semiconductor chip respectively, and
wherein the number of a sum of the second electrode pads is smaller than the number of a value of n times n.
2. The method for manufacturing the semiconductor device according to claim 1 ,
wherein the second semiconductor chip has a plurality of through electrodes, and the through electrodes are electrically coupled with the first electrode pads respectively.
3. The method for manufacturing the semiconductor device according to claim 2 ,
wherein a size of each of the first electrode pads is equal to a size of each of the second electrode pads.
4. The method for manufacturing the semiconductor device according to claim 2 ,
wherein a size of each of the first electrode pads is larger than a size of each of the second electrode pads.
5. The method for manufacturing the semiconductor device according to claim 2 ,
wherein a pitch of each of the first electrode pads is equal to a pitch of each of the second electrode pads.
6. The method for manufacturing the semiconductor device according to claim 2 ,
wherein a pitch of each of the first electrode pads is larger than a pitch of each of the second electrode pads.
7. The method for manufacturing the semiconductor device according to claim 2 ,
wherein the second s lace of the second semiconductor chip as a first side extend along a first direction in plan view,
wherein the second electrode pad group is located between the first side and the first electrode pad group in plan view, and
wherein the first direction is parallel to the rows in plan view.
8. The method for manufacturing the semiconductor device according to claim 2 ,
wherein the (a1) step is performed by imaging a recognition range including the recognition mark.
9. A method for manufacturing a semiconductor device, comprising the steps of:
(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,
wherein a first electrode pad group and a second electrode pad group are arranged over the second surface of the second semiconductor chip,
wherein the first electrode pad group includes a plurality of first electrode pads arranged in a matrix of n rows and m columns,
wherein n and m are greater than 1,
wherein the second electrode pad group includes a plurality of second electrode pads,
wherein a plurality of projection electrodes is arranged over the first surface of the first semiconductor chip,
the (a) step including the steps of:
(a1) recognizing the second electrode pad group as a recognition mark;
(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and
(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling with the plurality of first electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,
wherein the number of a sum of the second electrode pads is smaller than the number of a value of n times n, and
wherein the number of the sum of the second electrode pads is smaller than the number of the number of a value of m times m.
10. The method for manufacturing the semiconductor device according to claim 9 ,
wherein the second semiconductor chip has a plurality of through electrodes, and the through electrodes are electrically coupled with the first electrode pads respectively.
11. The method for manufacturing the semiconductor device according to claim 10 ,
wherein the second surface of the second semiconductor chip has a first side extend along a first direction in plan view,
wherein the second electrode pad group is located between the first side and the first electrode pad group in plan view, and
wherein the first direction is parallel to the rows in plan view.
12. The method for manufacturing the semiconductor device according to claim 11 ,
wherein a size of each of the first electrode pads is equal to a size of each of the second electrode pads.
13. The method for manufacturing the semiconductor device according to claim 11 ,
wherein a size of each of the first electrode pads is larger than a size of each of the second electrode pads.
14. The method for manufacturing the semiconductor device according to claim 11 ,
wherein a pitch of each of the first electrode pads is equal to a pitch of each of the second electrode pads.
15. The method for manufacturing the semiconductor device according to claim 11 ,
wherein a pitch of each of the first electrode pads is larger than a pitch of each of the second electrode pads.
16. The method for manufacturing the semiconductor device according to claim 11 ,
wherein the (a1) step is performed by imaging a recognition range including the recognition mark.