Nonvolatile memory device and method of fabricating the same

1. A method of fabricating a nonvolatile memory device, comprising:

forming a conductive layer for a gate electrode comprising at least one or more sacrificial layer patterns over a substrate;

forming a pipe connection gate electrode by selectively etching the conductive layer; and

forming etch stop layers including metal silicide over the pipe connection gate electrode other than some regions over the sacrificial layer patterns,

wherein forming the etch stop layers comprises:

forming a hard mask pattern covering parts of the pipe connection gate electrode; and

siliciding the exposed pipe connection gate electrode.

2. The method of claim 1 , wherein forming the conductive layer for a gate electrode comprises:

forming a first conductive layer for a gate electrode over the substrate;

forming grooves by selectively etching the first conductive layer for a gate electrode; and

forming sacrificial layer patterns within the grooves.

3. The method of claim 2 , further comprising forming a second conductive layer for a gate electrode over the first conductive layer and the sacrificial layer patterns, after forming the sacrificial layer patterns.

4. The method of claim 1 , wherein the pipe connection gate electrode is formed by separating the conductive layer on a block basis.

5. The method of claim 1 , wherein forming the etch stop layers comprising:

exposing the sacrificial layer patterns partially by selectively etching the pipe connection gate electrode;

forming a mask layer over the exposed sacrificial layer patterns; and

siliciding an upper part of the pipe connection gate electrode.

6. The method of claim 5 , wherein siliciding the upper part of the pipe connection gate electrode comprises:

forming a metal layer over the pipe connection gate electrode; and

annealing the substrate in which the metal layer is formed.

7. The method of claim 1 , wherein siliciding the exposed pipe connection gate electrode comprises:

forming a metal layer over the pipe connection gate electrode; and

annealing the substrate in which the metal layer is formed.

8. The method of claim 1 , wherein the sacrificial layer patterns comprise a material having an etch rate different from an etch rate of the conductive layer.

9. The method of claim 1 , wherein:

the substrate comprises a cell region and a peripheral region, and

forming the pipe connection gate electrode comprises forming peripheral gate electrodes by selectively etching the conductive layer in the peripheral region.

10. The method of claim 1 , further comprising:

alternately stacking a plurality of first material layers and a plurality of second material layers over the substrate in which the pipe connection gate electrode is formed, after forming the etch stop layers;

forming pairs of main channel holes where the sacrificial layer patterns are exposed by selectively etching the first material layers and the second material layers;

forming pipe channel holes for coupling the pairs of main channel holes by removing the sacrificial layer patterns; and

forming channel layers within the pairs of main channel holes and the pipe channel holes.

11. The method of claim 10 , wherein:

the first material layers are interlayer insulating layers, and

the second material layers are sacrificial layers.

12. The method of claim 10 , further comprising forming a memory layer on inner walls of the pairs of main channel holes and the pipe channel holes, after forming the pipe channel holes.

13. The method of claim 10 , further comprising:

forming slits in a depth that penetrates the plurality of second material layers on both sides of the main channel hole, after forming the channel layers;

removing the second material layers exposed by the slits; and

forming cell gate electrodes in spaces where the second material layers are removed.