Apparatus for lock detection suitable for fractional-N frequency synthesizer and method thereof
View Patent ↗Disclosed are an apparatus for lock detection suitable for a fractional-N frequency synthesizer and a method thereof. The lock detector for use in the fractional-N frequency synthesizer includes a delay unit delaying an N-divider output frequency clock based on an output value of a fraction ratio modulator, a lock detection unit outputting a lock detection signal by comparing a reference frequency clock with the N-divider output frequency clock delayed by the delay unit, a counter counting the number of lock detection signals received from the lock detection unit, and a controller issuing a command to output a lock identification signal based on the number of lock detection signals counted by the counter.
1. A lock detector for use in a fractional-N frequency synthesizer, comprising:
a delay unit delaying an N-divider output frequency clock based on an output value of a fractional ratio modulator;
a lock detection unit outputting a lock detection signal by comparing a reference frequency clock with the N-divider output frequency clock delayed by the delay unit;
a counter counting the number of lock detection signals received from the lock detection unit; and
a controller issuing a command to output a lock identification signal based on the number of lock detection signals counted by the counter.
2. The lock detector according to claim 1 , wherein the fractional ratio modulator is a ΣΔ Modulator.
3. The lock detector according to claim 1 , wherein the delay unit dynamically imparts a variable delay to the N-divider output frequency clock according to the output value of the fractional ratio modulator.
4. The lock detector according to claim 1 , wherein the variable delay is (D−m)×k (D and k being constants, m being an output value of the fractional ratio modulator).
5. The lock detector according to claim 1 , wherein the lock detection unit outputs the lock detection signal upon receiving a rising edge of the N-divider output frequency clock delayed by the delay unit in a section where the reference frequency clock is 1.
6. The lock detector according to claim 1 , wherein the controller issues a command to output the lock identification signal when the number of lock detection signals reaches a preset count value or more within a half cycle of the reference frequency.
7. A method of lock detection used in a fractional-N frequency synthesizer, comprising:
delaying an N-divider output frequency clock based on an output value of a fractional ratio modulator;
outputting a lock detection signal by comparing a reference frequency clock with the delayed N-divider output frequency clock;
counting the number of lock detection signals outputted; and
outputting a lock identification signal when the number of lock detection signals counted reaches a preset count value or more.
8. The method according to claim 7 , wherein the fractional ratio modulator is a ΣΔ Modulator.
9. The method according to claim 7 , wherein the delaying an N-divider output frequency clock comprises dynamically imparting a variable delay to the N-divider output frequency clock according to the output value of the fractional ratio modulator.
10. The method according to claim 7 , wherein the variable delay is a multiple of D−m (D being a constant and m being an output value of the fractional ratio modulator).
11. The method according to claim 7 , wherein the counting the number of lock detection signals comprises counting the number of lock detection signals upon receiving a rising edge of the delayed N-divider output frequency clock in a section where the reference frequency clock is 1.
12. The method according to claim 7 , wherein the outputting a lock identification signal comprises issuing a command to output the lock identification signal when the number of lock detection signals reaches the preset count value or more within a half cycle of the reference frequency.