POWER DEVICE
This disclosure discloses a power device. The power device comprises a substrate; a first semiconductor layer having a first band gap and disposed on the substrate; a second semiconductor layer having a second band gap being lager than the first band gap and disposed on the first semiconductor layer; a third semiconductor layer having a third band gap smaller than the second band gap layer and disposed on the second semiconductor layer; a source electrode disposed on the third semiconductor layer; a base electrode electrically connecting the source electrode; and a p-type metal-oxide layer disposed between the base electrode and the third semiconductor layer.
1 . A power device comprising:
a substrate;
a first semiconductor layer having a first band gap and disposed on the substrate;
a second semiconductor layer having a second band gap lager than the first band gap and disposed on the first semiconductor layer;
a third semiconductor layer having a third band gap smaller than the second band gap and disposed on the second semiconductor layer;
a source electrode disposed on the third semiconductor layer;
a base electrode electrically connecting to the source electrode; and
a p-type metal-oxide layer disposed between the base electrode and the third semiconductor layer.
2 . The power device of claim 1 , further comprising a drain electrode wherein the p-type metal-oxide layer is disposed between the source electrode and the drain electrode.
3 . The power device of claim 1 , further comprising a gate electrode disposed between the source electrode and the base electrode.
4 . The power device of claim 1 , wherein the p-type metal-oxide layer comprises NiO MoO CuO ZnO, or SnO 2 .
5 . The power device of claim 1 , wherein the p-type metal-oxide layer comprises a nano-rods structure.
6 . The power device of claim 1 , further comprising a two dimensional electron gas and a first interface disposed between the first semiconductor layer and second semiconductor layer wherein the two dimensional electron gas generates at the first interface while the power device is in a turn-on state.
7 . The power device of claim 1 , further comprising a two dimensional hole gas and a second interface disposed between the second semiconductor layer and third semiconductor layer wherein the two dimensional hole gas forms at the second interface while the power device is in a turn-on state.
8 . The power device of claim 1 , wherein the first semiconductor layer comprises In x Ga (1-x) N, wherein 0≦x<1.
9 . The power device of claim 1 , wherein the second semiconductor layer comprises Al y In z Ga (1-z) N, wherein 0<y<1, 0≦z<1.
10 . The power device of claim 1 , wherein the third semiconductor layer comprises In w Ga (1-w) N, wherein 0≦w<1.
11 . A power device, comprising:
a substrate;
a first semiconductor layer having a first lattice constant and disposed on the substrate;
a second semiconductor layer having a second lattice constant smaller than the first lattice constant and disposed on the first semiconductor layer;
a third semiconductor layer having a third lattice constant larger than the second lattice constant and disposed on the second semiconductor layer;
a source electrode disposed on the third semiconductor layer;
a base electrode electrically connecting to the source electrode; and
a p-type metal-oxide layer disposed between the base electrode and the third semiconductor layer.
12 . The power device of claim 11 , further comprising a drain electrode wherein the p-type metal-oxide layer is disposed between the source electrode and the drain electrode.
13 . The power device of claim 11 , further comprising a gate electrode disposed between the source electrode and the base electrode.
14 . The power device of claim 11 , wherein the p-type metal-oxide layer comprises NiO MoO CuO ZnO, or SnO 2 .
15 . The power device of claim 11 , wherein the p-type metal-oxide layer comprises a nano-rods structure.
16 . The power device of claim 11 , further comprising a two dimensional electron gas and a first interface disposed between the first semiconductor layer and second semiconductor layer wherein the two dimensional electron gas generates at the first interface while the power device is in a turn-on state.
17 . The power device of claim 11 , further comprising a two dimensional hole gas and a second interface disposed between the second semiconductor layer and third semiconductor layer wherein the two dimensional hole gas generates at the second interface while the power device is in a turn-on state.
18 . The power device of claim 11 , wherein the first semiconductor layer comprises In x Ga (1-x) N and 0≦x<1.
19 . The power device of claim 11 , wherein the second semiconductor layer comprises Al y In z Ga (1-z) N and 0<y<1, 0≦z<1.
20 . The power device of claim 11 , wherein the third semiconductor layer comprises In w Ga (1-w) N and 0≦w<1.