Thermodynamic-RAM technology stack
View Patent ↗A thermodynamic RAM technology stack, two or more memristors or pairs of memristors comprising AHaH (Anti-Hebbian and Hebbian) computing components, and one or more AHaH nodes composed of such memristor pairs that form at least a portion of the thermodynamic RAM technology stack. The levels of the thermodynamic-RAM technology stack include the memristor, a Knowm synapse, an AHaH node, a kT-RAM, kT-RAM instruction set, a sparse spike encoding, a kT-RAM emulator, and a SENSE Server.
1. Thermodynamic RAM (Random Access Memory), comprising:
an AHaH (Anti-Hebbian and Hebbian) circuit comprising synaptic inputs and at least one MSS (Metastable Switch) memristor, wherein said AHaH circuit is superimposed above at least one RAM core having bits, such that said synaptic inputs of said AHaH circuit are turned on in the same order in which said bits are set in said at least one RAM core; and
a plurality of memristive synapses comprising said synaptic inputs, said plurality of memristive synapses configured from said at least one MSS memristor, wherein said thermodynamic RAM performs an analog sum of currents based on an instruction set and said plurality of memristive synapses adapt physically by weight adaptation according to AHaH plasticity, which eliminates a need to compute and write memory updates, and wherein forward and reverse instructions thereof are paired to prevent weight saturation.
2. The thermodynamic RAM of claim 1 further comprising a digital emulation of said thermodynamic RAM.
3. The thermodynamic RAM of claim 2 wherein said thermodynamic RAM is emulated with CPU (Central Processing Unit) processors.
4. The thermodynamic RAM of claim 2 wherein said thermodynamic RAM is emulated with FPGA (Field Programmable Gate Array) processors.
5. The thermodynamic RAM of claim 2 wherein said thermodynamic RAM is emulated with GPU (Graphics Processing Unit) processors.
6. The thermodynamic RAM of claim 2 wherein said thermodynamic RAM is emulated with Epiphany processors.
7. The thermodynamic RAM of claim 2 wherein said thermodynamic RAM is emulated with custom CMOS circuitry.
8. The thermodynamic RAM of claim 1 wherein spike indices of a spike code are employed to directly index or activate said memristive synapses of said thermodynamic RAM.
9. The thermodynamic RAM of claim 1 further comprising multiple thermodynamic RAM including a plurality of thermodynamic RAM cores electrically coupled together to emulate a larger thermodynamic RAM core.
10. The thermodynamic RAM of claim 2 wherein spike indices of a spike code are employed to directly index or activate said memristive synapses of said thermodynamic RAM.
11. The thermodynamic RAM of claim 2 further comprising multiple thermodynamic RAM including a plurality of thermodynamic RAM cores electrically coupled together to emulate a larger thermodynamic RAM core.
12. The thermodynamic RAM of claim 7 wherein spike indices of a spike code are employed to directly index or activate said memristive synapses of said thermodynamic RAM.
13. The thermodynamic RAM of claim 7 further comprising multiple thermodynamic RAM including a plurality of thermodynamic RAM cores electrically coupled together to emulate a larger thermodynamic RAM core.