IP Library Granted Patent US 9,860,972
Granted Patent B2
US 9,860,972 · App. 14/723,662 · Granted Jan 2, 2018

Electrical connection interface for connecting electrical leads for high speed data transmission

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Quick Facts
Patent No.
US 9,860,972
App. No.
14/723,662
Granted
Jan 2, 2018
Kind
B2
Abstract

An electrical connection interface is provided. The electrical connection interface includes a first ground plane layer, a second ground plane layer, a first substrate and a second substrate. The second ground plane layer is positioned to overlap the first ground plane layer. The first substrate includes a first substrate conductive lead with a first interface region connected to and electrically insulated from the first ground plane layer. The second substrate includes a second substrate conductive lead with a second interface region connected to the first substrate conductive lead and the second ground plane layer. The second substrate conductive lead is electrically insulated from the second ground plane layer.

Claims (34)

1. An electrical connection interface for electrically coupling a printed circuit board to an electro-optical engine, the electrical connection interface comprising:

a first ground plane layer associated with the printed circuit board;

a second ground plane layer associated with the electro-optical engine;

a first substrate associated with the printed circuit board, the first substrate having a first substrate conductive lead with a first interface region connected to and electrically insulated from the first ground plane layer; and

a second substrate associated with the electro-optical engine, the second substrate having a second substrate conductive lead with a second interface region connected to the first interface region of the first substrate conductive lead, the second substrate conductive lead connected to and electrically insulated from the second ground plane layer;

wherein the second ground plane layer associated with the electro-optical engine includes clearance; and

wherein the first ground plane layer overlaps the second ground plane layer and a dimension of the clearance corresponds to a distance that the first ground plane layer overlaps the second ground plane layer.

2. The electrical connection interface according to claim 1 , wherein the first ground plane layer associated with the printed circuit board includes the clearance.

3. The electrical connection interface according to claim 1 , further comprising a grounding web and a plurality of clearances separated from each other by the grounding web.

4. The electrical connection interface according to claim 3 , wherein the grounding web includes a tapered region.

5. The electrical connection interface according to claim 1 , wherein the first substrate includes a pair of first substrate electrical leads including the first substrate conductive lead and the second substrate includes a pair of second substrate electrical leads including the second substrate conductive lead.

6. The electrical connection interface according to claim 5 , wherein the pair of first substrate electrical leads are adjacent to a common clearance.

7. The electrical connection interface according to claim 1 , wherein an impedance of the first substrate conductive lead matches a characteristic impedance of the second substrate conductive lead.

8. The electrical connection interface according claim 1 , wherein the first substrate or the second substrate includes a multilayer printed circuit board, a flexible printed circuit, or a ceramic circuit carrier.

9. The electrical connection interface according to claim 8 , wherein the first ground plane layer and the second ground plane layer are formed by a copper layer within or on a surface of the multilayer printed circuit board or the flexible printed circuit.

10. The electrical connection interface according to claim 1 , wherein the first ground plane layer and the second ground plane layer are electrically connected to each other by a contact point in an overlapping area.

11. The electrical connection interface according to claim 10 , wherein the contact point is adjacent to the first interface region and the second interface region.

12. The electrical connection interface according to claim 10 , wherein the clearance is adjacent to the first and second interface regions.

13. The electrical connection interface according to claim 12 , further comprising a grounding strip on an outer peripheral region of the clearance.

14. The electrical connection interface according to claim 1 , wherein the first substrate conductive lead is connected to the second substrate conductive lead by a solder connection, a press fit connection, or an adhesive.

15. The electrical connection interface according to claim 1 , the electro-optical engine comprising at least one optical transmitter or at least one optical receiver, wherein the second substrate conductive lead is electrically coupled to the optical transmitter or the optical receiver.

16. The electrical connection interface according to claim 15 , the electro-optical engine further comprising at least one driver or at least one amplifier, wherein the second substrate conductive lead is electrically coupled to the optical transmitter or the optical receiver by way of the driver or the amplifier.

17. An electrical connection interface comprising:

a printed circuit board (PCB) comprising:

a PCB ground plane layer; and

a first substrate having first substrate conductive leads with a first interface region electrically insulated from the first ground plane layer;

an electro-optical engine (E/O engine) comprising:

an E/O engine ground plane layer;

a second substrate having second substrate conductive leads with a second interface region connected to the first interface region of the first substrate conductive leads, the second substrate conductive leads electrically insulated from the E/O engine ground plane layer, the second substrate conductive leads including transmitting differential lines and the receiver differential lines;

optical transmitters positioned on the second substrate; and

optical receivers positioned on the second substrate;

wherein the optical transmitters are electrically coupled with the transmitting differential lines and the optical receivers are electrically coupled with the receiver differential lines

wherein the E/O engine ground plane layer includes clearance; and

wherein the PCB ground plane layer overlaps the E/O engine ground plane layer a distance corresponding to the size of the clearance.

Assignments (8)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2016
From: TYCO ELECTRONICS SVENSKA HOLDINGS AB
To: FINISAR CORPORATION
Reel/Frame 040471/0356 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2016
From: TYCO ELECTRONICS JAPAN G.K.
To: FINISAR CORPORATION
Reel/Frame 040471/0515 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: LAPIDOT, DORON
To: TYCO ELECTRONICS JAPAN G.K.
Reel/Frame 036988/0046 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2015
From: KAIKKONEN, ANDREI; LUNDQVIST, LENNART; SVENSSON, LARS-GOTE
To: TYCO ELECTRONICS SVENSKA HOLDINGS AB
Reel/Frame 036557/0580 →