Transistor with source and drain electrodes connected to an underlying light shielding layer
View Patent ↗According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
1. A semiconductor device comprising:
an insulating substrate;
an oxide semiconductor layer formed on the insulating substrate, the oxide semiconductor layer including a channel region, and a source region and a drain region disposed at the sides of the channel region;
a gate insulating film formed on the channel region;
a gate electrode formed on the gate insulating film;
an interlayer insulating film covering the gate electrode, the oxide semiconductor layer, and the gate insulating film;
a source electrode formed inside a contact hole which is provided in the interlayer insulating film and reaches the source region;
a drain electrode formed inside a contact hole which is provided in the interlayer insulating film and reaches the drain region; and
an interconnection layer made of a same material as a material of the gate electrode,
wherein the insulating substrate comprises a support substrate, an undercoat layer formed of an insulating material provided between the support substrate and the oxide semiconductor layer, and a light shielding layer between the support substrate and the oxide semiconductor layer to be opposed to the oxide semiconductor layer,
wherein a first contact hole provided in the interlayer insulating film reaches the light shielding layer,
a second contact hole provided in the interlayer insulating film reaches an upper surface of the interconnection layer made of the same material as that of the gate electrode, and the interconnection layer connects the first contact hole and the second contact hole to electrically connect to the light shielding layer.
2. The semiconductor device of claim 1 , wherein the oxide semiconductor layer has a thickness of 30 to 40 nm.