IP Library Granted Patent US 9,875,064
Granted Patent B2
US 9,875,064 · App. 14/727,069 · Granted Jan 23, 2018

Storage system architecture for improved data management

Inventor: Shinichi Kanno (Tokyo, JP)
Assignee: Toshiba Memory Corporation
G06F3/0679G06F3/0614G06F3/0644G06F12/0246
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Quick Facts
Patent No.
US 9,875,064
App. No.
14/727,069
Granted
Jan 23, 2018
Kind
B2
Abstract

According to one embodiment, a storage system includes a first storage and a controller which controls the first storage. The first storage includes a first group which includes a plurality of pages which are data write units and include first nonvolatile memories, and a first counter which counts the number of data writes to the first group. The controller determines whether all the pages in the first group has been written to or not.

Claims (27)

1. A storage system comprising:

a first storage including a plurality of pages which are data write units and include first nonvolatile memories, and a first counter which counts the number of writes to first pages of the plurality of pages, wherein each of the plurality of pages includes a flag bit indicating whether the page has been written to; and

a controller which controls the first storage,

wherein the controller is configured to:

write data to a page of the plurality of pages which includes a first flag bit set in a first state and change a state of the first flag bit from the first state to a second state; and

not write data to a page of the plurality of pages which includes a flag bit set in the second state, and

wherein when the flag bits of the first pages are set in the second state, the controller increments a value of the first counter and returns the states of the flag bits of the first pages from the second state to the first state.

2. The storage system of claim 1 , wherein the first storage further includes

a second counter which counts the number of writes to second pages of the plurality of pages, and

wherein when the flag bits of the second pages are set in the second state, the controller increments a value of the second counter and returns the states of the flag bits of the second pages from the second state to the first state.

3. The storage system of claim 2 , wherein the controller refers to the numbers of writes counted by the first and second counters to select one of the first pages and the second pages, in which the number of writes is smaller than that to the other, as target pages to be written to.

4. The storage system of claim 1 , further comprising a second storage including second nonvolatile memories.

5. The storage system of claim 4 ,

wherein the first nonvolatile memories are memories storing data which is to be corrupted when data is read from the first nonvolatile memories, and

wherein the controller is configured to:

read data from a first nonvolatile memory at a first address which is included in the first nonvolatile memories,

determine whether the read data is to be written back to the first storage, and

write, if determining that the read data is not to be written back to the first storage, the read data to a second nonvolatile memory at a second address in the second storage.

6. The storage system of claim 5 , wherein if determining that the read data is to be written back to the first storage, the controller is configured to write the read data to a first nonvolatile memory at a third address in the first storage.

7. The storage system of claim 4 , further comprising a third storage which stores data in a nonvolatile manner, and has a data capacity larger than that of the second storage.

8. The storage system of claim 7 , wherein the third storage includes an HDD.

9. The storage system of claim 4 , wherein the second storage includes NAND flash memories.

10. The storage system of claim 1 , further comprising an address conversion table which indicates a correspondence between logical addresses managed by a host and physical addresses managed by the storage system.

11. The storage system of claim 1 , wherein the first nonvolatile memory includes:

a resistance change element whose resistance value varies in accordance with a flowing direction of current in the resistance change element; and

a switching element provided to switch the flowing direction of the current in the resistance change element.

12. The storage system of claim 1 , wherein the first storage includes MRAMs.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043529/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2015
From: KANNO, SHINICHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035755/0754 →
Continuity (2)
Provisional Application 62131794 · Mar 11, 2015
Related Publication 20160267002A1 · Sep 15, 2016