IP Library Granted Patent US 9,780,189
Granted Patent B2
US 9,780,189 · App. 14/730,092 · Granted Oct 3, 2017

Transistor with contacted deep well region

Inventor: George Imthurn (San Diego, CA)
Assignee: Silanna Asia Pte Ltd
H01L29/66492H01L21/2253H01L21/283H01L29/0692H01L29/1095H01L29/402H01L29/4238H01L29/66659H01L29/7833H01L29/7835
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Quick Facts
Patent No.
US 9,780,189
App. No.
14/730,092
Granted
Oct 3, 2017
Kind
B2
Abstract

Various methods and devices that involve body contacted transistors are disclosed. An exemplary method comprises forming a gate on a planar surface of a semiconductor wafer. The gate covers a channel of a first conductivity type that is opposite to a second conductivity type. The method also comprises implanting a body dose of dopants on a source side of the gate using the gate to mask the body dose of dopants. The body dose of dopants spreads underneath the channel to form a deep well. The body dose of dopants has the first conductivity type. The method also comprises implanting, subsequent to implanting the body dose of dopants, a source dose of dopants on the source side of the gate to form a source. The method also comprises forming a source contact that is in contact with the deep well at the planar surface of the semiconductor wafer.

Claims (29)

1. A method of forming a transistor, wherein the method comprises:

between a source side and a drain side of the transistor forming a gate for the transistor on a surface of a wafer;

forming a dielectric overlayer over the gate, the source side, and the drain side of the transistor;

patterning the dielectric overlayer with an asymmetric pattern that covers the gate and the drain side of the transistor, and exposes a region of the surface of the wafer on the source side of the transistor;

implanting a body dose of dopants into the exposed region of the surface of the wafer, wherein the body dose of dopants spreads underneath the gate to form a deep well for the transistor, and wherein the body dose of dopants has a first conductivity type;

implanting, subsequent to implanting the body dose of dopants, a source dose of dopants on the source side of the transistor to form a source region for the transistor;

implanting, subsequent to implanting the source dose of dopants, a body contact dose of dopants into the exposed region of the surface of the wafer, wherein the body contact dose of dopants forms a body contact region of the deep well that extends from the surface of the wafer to below the source region; and

performing only one of: (i) forming on the surface of the wafer a source contact for the transistor, wherein the source contact is in physical contact with the source region and the body contact region of the deep well; and (ii) forming a source contact and a gate shield for the transistor that are in physical contact with each other, wherein the gate shield is in physical contact with the source region and the body contact region of the deep well at the surface of the wafer.

2. The method of claim 1 , further comprising:

depositing a photoresist on the exposed region of the surface of the wafer; and

patterning the photoresist to form a channel width pattern that extends contiguously along a width of the transistor;

wherein the implanting of the body contact dose of dopants utilizes the contiguous channel width pattern such that the source region isolates a channel of the transistor from the body contact region.

3. The method of claim 1 , further comprising:

depositing a photoresist on the exposed region of the surface of the wafer; and

patterning the photoresist to form a finger pattern having a plurality of strips that extend away from the gate;

wherein the implanting of the source dose of dopants utilizes the finger pattern to form a plurality of fingers along a width of the transistor.

4. The method of claim 1 , further comprising:

implanting a lightly doped drain dose of dopants into the surface of the wafer on the drain side of the transistor to form a lightly doped drain region;

wherein the deep well has an opposite conductivity type than the lightly doped drain region and the source region; and

wherein a dopant concentration of the lightly doped drain region is less than a dopant concentration of the source region.

5. The method of claim 1 , wherein:

the body contact dose of dopants is heavier than the source dose of dopants; and

the body contact dose of dopants is less than ten times as heavy as the source dose of dopants.

6. The method of claim 5 , wherein:

the exposed region of the surface of the wafer receives both the source dose of dopants and the body contact dose of dopants; and

the exposed region of the surface of the wafer has a width that is less than 1 micron measured normal to a width of the transistor.

7. The method of claim 1 , wherein:

the implanting of the body contact dose of dopants is conducted using less than 20 keV; and

a surface of the body contact region that is located on the surface of the wafer is located entirely within 1 micron of a gate electrode of the gate.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE FROM SILANNA ASIA PTD LDT. TO SILANNA ASIA PTE LTD. PREVIOUSLY RECORDED AT REEL: 036389 FRAME: 0283. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 4, 2017
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: SILANNA ASIA PTE LTD
Reel/Frame 041245/0222 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS PATENT NUMBER 9029901 TO THE CORRECT PATENT NO. 9029201 AS PREVIOUSLY RECORDED ON REEL 036812 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST AGAINST ALL PATENTS SET FORTH HEREIN. Recorded Oct 20, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036907/0785 →
TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST (PATENTS) Recorded Oct 7, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036812/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2015
From: IMTHURN, GEORGE
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 036543/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2015
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: SILANNA ASIA PTD LTD.
Reel/Frame 036389/0283 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2015
From: IMTHURN, GEORGE
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 035781/0506 →
Continuity (1)
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