Resource sharing in a telecommunications environment
View Patent ↗A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.
1. A transceiver comprising:
a memory comprising a plurality of bytes, X, wherein X is a number,
wherein the memory can be shared between an interleaver function associated with a transmit latency path and a deinterleaver function associated with a receive latency path, wherein the sharing comprises using a first portion of the memory for the interleaver function and simultaneously using a second portion of the memory, different than the first portion, for the deinterleaver function, and the first and second portions are configurable such that one or more bytes of the memory can be used by the interleaver function at one particular time and the same one or more bytes of the memory can be used by the deinterleaver function at a second time, different than the first time, and
wherein the transceiver is operable to transmit a message or receive a message, wherein the message comprises information that is used to determine a maximum number of bytes, Y, of the memory, for the interleaver function and information is used to determine a maximum number of bytes, Z, of the memory, for the deinterleaver function, wherein Y and Z are positive numbers and wherein Y+Z is less than or equal to X.
2. The transceiver of claim 1 , wherein the value of Y and Z vary depending on at least one impulse noise protection value.
3. The transceiver of claim 1 , wherein the value of Y and Z vary depending on at least one delay value.
4. The transceiver of claim 1 , wherein the value of Y and Z vary depending on at least one data rate value.
5. The transceiver of claim 1 , wherein the transceiver further comprises a transmitter portion, the transmitter portion including a framer, a coder and an interleaver, wherein the framer is linked to the coder and the coder is linked to the interleaver.
6. The transceiver of claim 1 , wherein the transceiver further comprises a receiver portion, the receiver portion including a deframer, a decoder and a deinterleaver, wherein the deinterleaver is linked to the decoder and the decoder is linked to the deframer.
7. The transceiver of claim 1 , wherein the memory is connected to at least one coder.
8. The transceiver of claim 1 , wherein the memory is connected to at least one decoder.
9. The transceiver of claim 1 , further comprising a shared processing module connected to at least one coder.
10. The transceiver of claim 1 , further comprising a shared processing module connected to at least one decoder.
11. A method in a multicarrier transceiver comprising a memory comprising a plurality of bytes X, wherein X is a number, the method comprising:
transmitting a message, using multicarrier modulation, or receiving a message, using multicarrier modulation, wherein the message comprises information that is used to determine a maximum number of bytes, Y, of the memory, for an interleaver function associated with a transmit latency path, and information that is used to determine a maximum number of bytes, Z, of the memory, for a deinterleaver function associated with a receive latency path, wherein Y and Z are poitive numbers and wherein Y+Z is less than or equal to X,
wherein the memory can be shared between the interleaver function and the deinterleaver function, wherein the sharing comprises using a first portion of the memory for the interleaver function and simultaneously using a second portion of the memory, different than the first portion, for the deinterleaver function, and the first and second portions are configurable such that one or more bytes of the memory can be used by the interleaver function at one particular time and the same one or more bytes can be used by the deinterleaver function at a second time, different than the first time.
12. The method of claim 11 , wherein the value of Y and Z vary depending on at least one impulse noise protection value.
13. The method of claim 11 , wherein the value of Y and Z vary depending on at least one delay value.
14. The method of claim 11 , wherein the value of Y and Z vary depending on at least one data rate value.
15. The method of claim 11 , wherein the transceiver comprises a transmitter portion, the transmitter portion including a framer, a coder and an interleaver, wherein the framer is linked to the coder and the coder is linked to the interleaver.
16. The method of claim 11 , wherein the transceiver comprises a receiver portion, the receiver portion including a deframer, a decoder and a deinterleaver, wherein the deinterleaver is linked to the decoder and the decoder is linked to the deframer.
17. The method of claim 11 , wherein the memory is connected to at least one coder.
18. The method of claim 11 , wherein the memory is connected to at least one decoder.
19. The method of claim 11 , wherein the transceiver further comprises a shared processing module connected to at least one coder.
20. The method of claim 11 , wherein the transceiver further comprises a shared processing module connected to at least one decoder.
21. A transceiver comprising:
a transmitter operable to transmit a message, wherein the message comprises information that is used to determine a maximum number of bytes for an interleaver function associated with a transmit latency path and information that is used to determine a maximum number of bytes for a deinterleaver function associated with a receive latency path, and wherein the information that is used to determine the maximum number of bytes for the interleaver function and the information that is used to determine the maximum number of bytes for the deinterleaver function varies depending on at least one data rate value.
22. The transceiver of claim 21 , wherein the transceiver further comprises a transmitter portion, the transmitter portion including a framer, a coder and an interleaver, wherein the framer is linked to the coder and the coder is linked to the interleaver.
23. The transceiver of claim 21 , wherein the transceiver further comprises a receiver portion, the receiver portion including a deframer, a decoder and a deinterleaver, wherein the deinterleaver is linked to the decoder and the decoder is linked to the deframer.
24. The transceiver of claim 21 , wherein the memory is connected to at least one coder.
25. The transceiver of claim 21 , wherein the memory is connected to at least one decoder.
26. The transceiver of claim 21 , further comprising a shared processing module connected to at least one coder.
27. The transceiver of claim 21 , further comprising a shared processing module connected to at least one decoder.
28. A transceiver comprising:
a transmitter operable to transmit a message, wherein the message comprises information that is used to determine a maximum number of bytes for an interleaver function associated with a transmit latency path, and information that is used to determine a maximum number of bytes for a deinterleaver function associated with a receive latency path, and wherein the information that is used to determine the maximum number of bytes for the interleaver function and the information that is used to determine the maximum number of bytes for the deinterleaver function varies depending on at least one impulse noise protection value.
29. A transceiver comprising:
a transmitter operable to transmit a message, wherein the message comprises information that is used to determine a maximum number of bytes for an interleaver function associated with a transmit latency path, and information that is used to determine a maximum number of bytes for a deinterleaver function associated with a receive latency path, and wherein the information that is used to determine the maximum number of bytes for the interleaver function and the information that is used to determine the maximum number of bytes for the deinterleaver function varies depending on at least one delay value.