ADAPTABLE VIDEO ARCHITECTURES
Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.
1 - 20 . (canceled)
21 . A device comprising:
at least one processor circuit configured to:
obtain an original pixel block of a video stream;
decompose the original pixel block into a plurality of sub-blocks;
process each of the sub-blocks through a plurality of pipeline elements, a first sub-block of the sub-blocks being processed through a first pipeline element of the plurality of pipeline elements and a second sub-block of the sub-blocks being processed by a second pipeline element of the plurality of pipeline elements that is distinct from the first pipeline element; and
recompose the processed sub-blocks to form a processed pixel block.
22 . The device of claim 21 , wherein at least one processor circuit is configured to process each of the sub-blocks through one of the plurality of pipeline elements in parallel.
23 . The device of claim 21 , wherein each of the sub-blocks is transcoded by the plurality of pipeline elements.
24 . The device of claim 21 , wherein each of the sub-blocks is processed through a different one of the plurality of pipeline elements.
25 . The device of claim 21 , wherein a third sub-block of the sub-blocks is processed through the first pipeline element after the first sub-block of the sub-blocks is processed through the first pipeline element.
26 . The device of claim 21 , wherein a size of the original pixel is indicated by a standard.
27 . The device of claim 21 , wherein the at least one processor circuit is further configured to:
receive a frame of the video stream;
separate the frame of the video stream into a plurality of original pixel blocks; and
obtain the original pixel block from the plurality of original pixel blocks.
28 . The device of claim 27 , wherein the at least one processor circuit is further configured to:
decompose each of the plurality of original pixel blocks into the plurality of sub-blocks;
process each of the sub-blocks of each of the plurality of original pixel blocks through the plurality of pipeline elements; and
recompose the processed sub-blocks of each of the plurality of original pixel blocks to form a plurality of processed pixel blocks.
29 . The device of claim 28 , wherein the at least one processor circuit is further configured to:
recompose the plurality of processed pixel blocks to form a processed frame of the video stream.
30 . A method comprising:
obtaining an original pixel block of a video stream;
decomposing the original pixel block into a plurality of sub-blocks;
processing each of the sub-blocks through at least one pipeline element, the at least one pipeline element cycling through at least two of the sub-blocks; and
recomposing the processed sub-blocks to form a processed pixel block.
31 . The method of claim 30 , wherein the at least one pipeline element comprises a plurality of interconnected pipeline elements.
32 . The method of claim 31 , wherein a first pipeline element of the plurality of interconnected pipeline elements cycles through a first subset of the plurality of sub-blocks while a second pipeline element of the plurality of interconnected pipeline elements cycles through a second subset of the plurality of sub-blocks.
33 . The method of claim 30 , wherein the at least one pipeline element is configured to transcode each of the sub-blocks.
34 . The method of claim 30 , wherein a size of the original pixel is indicated by a standard.
35 . The method of claim 30 , further comprising:
receiving a frame of the video stream;
separating the frame of the video stream into a plurality of original pixel blocks; and
obtaining the original pixel block from the plurality of original pixel blocks.
36 . The method of claim 35 , further comprising:
decomposing each of the plurality of original pixel blocks into the plurality of sub-blocks;
processing each of the sub-blocks of each of the plurality of original pixel blocks through the at least one pipeline element;
recomposing the processed sub-blocks of each of the plurality of original pixel blocks to form a plurality of processed pixel blocks; and
recomposing the plurality of processed pixel blocks to form a processed frame of the video stream.
37 . A computer program product comprising instructions stored in at least one non-transitory computer-readable storage medium, the instructions comprising:
instructions to receive an original frame of a video stream;
instructions to separate the original frame of the video stream into a plurality of original pixel blocks;
instructions to decompose each of the plurality of original pixel blocks into a plurality of sub-blocks;
instructions to process each of the sub-blocks of each of the plurality of original pixel blocks through at least one pipeline element;
instructions to recompose the processed sub-blocks of each of the plurality of original pixel blocks to form a plurality of processed pixel blocks; and
instructions to recompose the plurality of processed pixel blocks to form a processed frame of the video stream.
38 . The computer-readable storage medium of claim 37 , wherein at least two of the sub-blocks of at least one of the plurality of original pixel blocks are processed through the at least one pipeline element in parallel.
39 . The computer-readable storage medium of claim 37 , wherein the at least one pipeline element transcodes each of the sub-blocks of each of the plurality of original pixel blocks.
40 . The computer-readable storage medium of claim 37 , wherein a size of each of the plurality of original pixel blocks is defined by a video coding standard.