Semiconductor device including a redistribution layer

1. A semiconductor device comprising:

a first redistribution layer configured to allow for input and output of a first signal through the first redistribution layer;

a second redistribution layer configured to allow for input and output of a second signal through the second redistribution layer;

a first input/output (I/O) unit configured to input and output the first signal or the second signal through the first I/O unit;

a first selection unit configured to selectively couple a connection among the first redistribution layer, the second redistribution layer, and the first I/O unit in response to a logic level of a first selection signal; and

a first selection signal generation unit configured to generate the first selection signal,

wherein the first selection signal generation unit includes a first selection signal driving unit configured to drive the first selection signal in response to a signal of a first pad and a power-ON signal,

wherein the first selection signal driving unit includes:

a first pull-up driving element coupled between a power-supply voltage terminal and a first node, and configured for being controlled by the power-ON signal;

a first pull-down driving element coupled between an output terminal of the first pad and a ground voltage terminal, and including a gate terminal coupled to the first node;

a first inverter coupled between an output terminal of the first pad and the first node; and

a second inverter configured to output the first selection signal by inverting an output signal of the first node.

2. The semiconductor device according to claim 1 , wherein the first selection unit selects the first redistribution layer when the first selection signal is at a first logic level, and selects the second redistribution layer when a second selection signal is at a second logic level different from the first logic level.

3. The semiconductor device according to claim 1 , wherein the first I/O unit includes:

a first receiver configured to output a signal received from the first selection unit; and

a first transceiver configured to output an external input signal to the first selection unit.

4. The semiconductor device according to claim 1 , wherein the first I/O unit includes:

a second transceiver and a second receiver configured to input/output the first signal of the first redistribution layer received from the first selection unit; and

a third transceiver and a third receiver configured to input/output the second signal of the second redistribution layer received from the first selection unit.

5. The semiconductor device according to claim 1 , wherein the first selection signal generation unit further comprising:

a first power line configured to provide a power-supply voltage; and

the first pad configured to provide a floating state.

6. The semiconductor device according to claim 1 , wherein the first selection signal driving unit outputs the first selection signal of a low level when the power-ON signal is at a low level, and maintains the first selection signal of a low level when the power-ON signal transitions to a high level.

7. The semiconductor device according to claim 1 , further comprising:

a third redistribution layer configured to allow for input and output of a third signal through the third redistribution layer;

a fourth redistribution layer configured to allow for input and output of a fourth signal through the fourth redistribution layer, and coupled to the second redistribution layer through a through silicon via (TSV);

a second input/output (I/O) unit configured to input and output the third signal or the fourth signal through the second I/O unit;

a second selection unit configured to selectively couple the third redistribution layer, the fourth redistribution layer, and input/output (I/O) nodes of the second I/O unit in response to a logic level of a second selection signal; and

a second selection signal generation unit configured to generate the second selection signal.

8. The semiconductor device according to claim 7 , wherein the second selection unit selects a third redistribution layer when the second selection signal is at a first level, and selects a fourth redistribution layer when the second selection signal is at a second level different from the first logic level.

9. The semiconductor device according to claim 7 , wherein the second I/O unit includes:

a fourth receiver configured to output a signal received from the second selection unit; and

a fourth transceiver configured to output an external input signal to the second selection unit.

10. The semiconductor device according to claim 7 , wherein the second I/O unit includes:

a fifth transceiver and a fifth receiver configured to input/output the third signal of the third redistribution layer received from the second selection unit; and

a sixth transceiver and a sixth receiver configured to input/output the fourth signal of the fourth redistribution layer received from the second selection unit.

11. The semiconductor device according to claim 7 , wherein the second selection signal generation unit includes:

a third power line coupled to a first power line of the first selection signal generation unit through the through silicon via (TSV);

a third pad coupled to the first power line through the TSV; and

a third selection signal driving unit configured to drive the second selection signal in response to a signal of the third pad and a power-ON signal.

12. The semiconductor device according to claim 11 , wherein the third selection signal driving unit includes:

a third pull-up driving element coupled between a power-supply voltage terminal and a third node, and configured for being controlled by the power-ON signal;

a third pull-down driving element coupled between an output terminal of the third pad and a ground voltage terminal, and including a gate terminal coupled to the third node;

a fifth inverter coupled between an output terminal of the third pad and the third node; and

a sixth inverter configured to output the second selection signal by inverting an output signal of the third node.

13. The semiconductor device according to claim 11 , wherein the third selection signal driving unit outputs the second selection signal of a low level when the power-ON signal is at a low level, and transitions the second selection signal to a high level in response to a signal received from the third pad when the power-ON signal transitions to a high level.

14. The semiconductor device according to claim 11 , wherein the third selection signal driving unit includes:

a fourth pull-up driving element coupled between a power-supply voltage terminal and an output terminal of the third pad, and configured for being controlled by an output signal of a fourth node;

a fourth pull-down driving element coupled between the fourth node and a ground voltage terminal, and configured to receive an inversion signal of the power-ON signal through a gate terminal;

a seventh inverter coupled between an output terminal of the third pad and the fourth node; and

an eighth inverter configured to output the second selection signal by inverting an output signal of the fourth node.

15. The semiconductor device according to claim 11 , wherein the third selection signal driving unit outputs the second selection signal of a high level when an inversion signal of the power-ON signal is at a high level, and transitions the second selection signal to a low level in response to a signal received from the third pad when the inversion signal of the power-ON signal transitions to a low level.

16. The semiconductor device according to claim 7 , wherein the through silicon via (TSV) is configured to couple the second redistribution layer formed in a lower chip to the fourth redistribution layer formed in an upper chip.

17. A semiconductor device comprising:

a first redistribution layer configured to allow for input and output of a first signal through the first redistribution layer;

a second redistribution layer configured to allow for input and output of a second signal through the second redistribution layer;

a first input/output (I/O) unit configured to input and output the first signal or the second signal through the first I/O unit;

a first selection unit configured to selectively couple a connection among the first redistribution layer, the second redistribution layer, and the first I/O unit in response to a logic level of a first selection signal; and

a first selection signal generation unit configured to generate the first selection signal,

wherein the first selection signal generation unit includes a second selection signal driving unit configured to drive the first selection signal in response to a signal of a second pad and a power-ON signal,

wherein the second selection signal driving unit includes:

a second pull-up driving element coupled between a power-supply voltage terminal and an output terminal of the second pad, and configured for being controlled by an output signal of a second node;

a second pull-down driving element coupled between an output terminal of the second node and a ground voltage terminal, and configured to receive an inversion signal of the power-ON signal through a gate terminal;

a third inverter coupled between an output terminal of the second pad and the second node; and

a fourth inverter configured to output the first selection signal by inverting an output signal of the second node.

18. The semiconductor device according to claim 17 , wherein the second selection signal driving unit outputs the first selection signal of a high level when the inversion signal of the power-ON signal is at a high level, and maintains the first selection signal at a high level when the inversion signal of the power-ON signal transitions to a low level.

19. The semiconductor device according to claim 17 , wherein the first selection signal generation unit further comprising:

a second power line configured to provide a ground voltage; and

the second pad configured to provide a floating state.