Test apparatus, test system and operating method of test apparatus
View Patent ↗A test system may include: a vector storage unit suitable for storing a first test vector corresponding to a first test operation; a test target suitable for performing a test operation corresponding to the test vector stored in a vector storage unit; a comparison unit suitable for comparing a first test result to an expected value to output a first test result value, wherein the first test result is transferred from the test target as a result of the first test operation based on the first test vector; and a vector control unit suitable for modifying the first test vector to generate a second test vector corresponding to a second test operation.
1. A test system comprising:
a vector storage unit suitable for storing a first test vector corresponding to a first test operation;
a test target suitable for performing the first test operation corresponding to the first test vector stored in the vector storage unit;
a comparison unit suitable for comparing a first test result to an expected value to determine whether the test target is normal, wherein the first test result is transferred from the test target as a result of the first test operation based on the first test vector; and
a vector control unit suitable for modifying the first test vector to generate a second test vector corresponding to a second test operation,
wherein the test target is suitable for performing the second test operation corresponding to the second test vector,
wherein the first and second test vectors include a plurality of detection voltages and a select signal for selectively outputting the detection voltages, and the vector control unit controls the select signal to modify the first test vector.
2. The test system of claim 1 , wherein a part of bits that form the first test vector is modified to generate the second test vector.
3. The test system of claim 1 , further comprising an expected value control unit suitable for modifying the expected value to correspond to the second test operation.
4. The test system of claim 3 , wherein a part of bits that form the expected value is modified when the expected value is modified.
5. The test system of claim 1 , further comprising a defect detection unit suitable for detecting a defect of the first test vector stored in the vector storage unit to generate a control signal for modifying the first test vector stored in the vector storage unit to generate the second test vector.
6. The test system of claim 1 , wherein the test target includes a plurality of transmission lines for coupling a plurality of external input/output terminals to an internal circuit, and
the internal circuit includes:
a buffering unit suitable for buffering a test vector transmitted through the transmission lines; and
a defective line detection unit suitable for detecting coupling states of the transmission lines based on an output signal of the buffering unit.
7. The test system of claim 1 , wherein the detection voltages have different voltage levels.
8. The test system of claim 1 , wherein the test target includes a plurality of transmission lines for coupling a plurality of external input/output terminals to an internal circuit, and
the internal circuit includes a selection unit suitable for selectively outputting the detection voltages transmitted through the transmission lines based on the select signal.
9. An operating method of a test apparatus, comprising:
initializing the test apparatus to generate a first test vector;
performing a first test operation corresponding to the first test vector;
modifying the first test vector to generate a second test vector; and
performing a second test operation corresponding to the second test vector,
wherein the first test vector includes a plurality of detection voltages and a select signal for selectively outputting the detection voltages, and the second test vector is obtained by modifying the select signal.
10. The operating method of claim 9 , wherein, in the modifying of the first test vector, a part of bits that form the first test vector is modified.
11. The operating method of claim 9 , further comprising:
comparing the first test vector to a first expected value to determine whether a test target is normal; and
comparing the second test vector to a second expected value to determine whether the test target is normal.
12. The operating method of claim 11 , wherein the first expected value corresponding to the first test operation is generated when the test apparatus is initialized.
13. The operating method of claim 11 , further comprising:
generating the second expected value by modifying the first expected value.
14. A test system comprising:
a semiconductor device including a detection unit suitable for receiving a test vector and detecting a coupling state of a transmission line coupled to the semiconductor device, based on the test vector; and
a test apparatus suitable for modifying the test vector based on a design type information of the detection unit and, based on a detection result,
wherein the test vector includes a plurality of detection voltages and a select signal, and the detection unit outputs a corresponding detection voltage from among the plurality of detection voltages based on the select signal which selects the detection voltages.
15. The test system of claim 14 , wherein the test vector includes multiple bits, and
the test apparatus modifies defective bits of the test vector to output a repaired test vector.
16. The test system of claim 15 , wherein the test apparatus includes a vector control unit suitable for modifying a part of the bits.
17. The test system of claim 15 , wherein the test apparatus includes a vector control unit suitable for modifying a select signal.
18. The test system of claim 14 , wherein the transmission line is coupled between an internal circuit and a plurality of external input/output terminals of the semiconductor device.
19. A test apparatus comprising:
a vector storage unit suitable for storing a first test vector corresponding to a first test operation, and transferring the first test vector to a test target;
a comparison unit suitable for comparing a first test result to an expected value to determine whether the test target is normal, wherein the first test result is transferred from the test target as a result of the first test operation based on the first test vector; and
a vector control unit suitable for modifying the first test vector to generate a second test vector corresponding to a second test operation,
wherein the vector storage unit performs the second test operation corresponding to the second test vector,
wherein the first and second test vectors include detection voltages and a select signal for selectively outputting the detection voltages, and the vector control unit controls the select signal to modify the first test vector.
20. The test apparatus of claim 19 , wherein a part of bits that form the first test vector is modified to generate the second test vector.
21. The test apparatus of claim 19 , further comprising an expected value control unit suitable for modifying the expected value to correspond to the second test operation.
22. The test apparatus of claim 21 , wherein a part of bits that form the expected value is modified when the expected value is modified.
23. The test apparatus of claim 22 , further comprising a defect detection unit suitable for detecting a defect of a test vector stored in the vector storage unit to generate a control signal for modifying the test vector stored in the vector storage unit.
24. The test apparatus of claim 16 , wherein the detection voltages have different voltage levels.