Clock recovery method and clock recovery arrangement for coherent polarization multiplex receivers
View Patent ↗Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.
1. A clock recovery method for optical coherent polarization multiplex receivers,
comprising the steps of
coherently demodulating a received polarization multiplex signal and deriving orthogonal signal components,
sampling and converting the orthogonal signal components into digital component values,
feeding said digital component values to a same equalizer, said equalizer being configured to effectively reverse the effect of polarization mixing of the received orthogonal signals for one specific polarization mixing angle,
deriving phase error values from output values of said equalizer and from the digital component values,
calculating two resulting phase error values, wherein each resulting phase error value is calculated from
at least one phase error value derived from output values of said equalizer and
at least one phase error value derived from the digital component values,
deriving a first oscillator control signal and a second oscillator control signal from said resulting phase error values,
controlling a first controllable oscillator generating a sample signal for sampling a corresponding one of said orthogonal signal components or re-sampling the digital component values based on said first oscillator control signal, and
controlling a second controllable oscillator generating a sample signal for sampling a corresponding one of said orthogonal signal components or re-sampling the digital component values based on said second oscillator control signal.
2. The clock recovery method according to claim 1 , wherein said resulting phase error values are calculated by combining phase error values directly derived from the digital component values with phase error values derived from equalizer output values.
3. The clock recovery method according to claim 1 , wherein said two resulting phase error values are resulting phase error values for two separate clock recovery loops.
4. The clock recovery method according to claim 1 , comprising the step of
generating phase error values according to
X PEi [n]=XI Ei [n− ½]( XI Ei [n]−XI Ei [n− 1])+ XQ Ei [n− ½]( XQ E [n]−XQ Ei [n− 1]), Y PEi [n]=YI Ei [n− ½]( YI Ei [n]−YI Ei [n− 1])+ YQ Ei [n− ½]( YQ Ei [n]−YQ Ei [n− 1]),
wherein XI Ei , XQ Ei ; YI Ei , YQ Ei , resemble equalizer output values or digital component values; n is an integer resembling a sample instant; and i =1, 2, . . . , N.
5. A clock recovery arrangement for an optical coherent polarization multiplex receiver with a first phase locked loop and a second phase locked loop deriving respective sample signals, each of the first phase locked loop and the second phase locked loop including a phase error detector unit receiving sampled component values, a loop filter, and a controllable oscillator,
comprising
a fixed equalizer receiving sampled component values and outputting equalizer output values, said equalizer being configured to effectively reverse the effect of polarization mixing of the received orthogonal signals for one specific polarization mixing angle,
a plurality of phase error detectors receiving equalizer output values or sampled component values and generating phase error values, and
for each of the first phase locked loop and the second phase locked loop, means for combining phase error values to derive two resulting phase error values, wherein each resulting phase error value is calculated from
at least one phase error value derived from output values of said fixed equalizer and
at least one phase error value derived from the sampled component values, said resulting phase error values for controlling at least one controllable oscillator of the respective phase locked loop.
6. The clock recovery arrangement according to claim 5 , wherein
the phase error detector unit of the first phase locked loop generates a first control signal,
the first phase locked loop receives said first control signal and generates a first sample signal for sampling x signal components, and
the phase error detector unit of the second phase locked loop generates a second control signal, and
the second phase locked loop receives said second control signal and generates a second sample signal for sampling y signal components.