Successive approximation register analog-to-digital converter
View Patent ↗Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
1. A method of converting an analog input value to a digital output code, comprising:
selecting a settling time for a digital-to-analog converter based on a bit position of the digital output code being determined;
comparing an analog reference value generated by the digital-to-analog converter in response to expiration of the selected settling time for the digital-to-analog converter; and
updating the bit position of the digital output code based on a comparison result of said comparing.
2. The method of claim 1 , wherein said updating comprises updating a bit position after expiration of a comparator settling time.
3. The method of claim 2 , wherein said selecting comprises selecting a greater settling time for a most significant bit of the digital output code than for a least significant bit of the digital output code.
4. The method of claim 2 , wherein said selecting comprises selecting a greater settling time for a most significant bit of the digital output code than for a second most significant bit of the digital output code.
5. The method of claim 2 , wherein said selecting comprises selecting a greater settling time for one bit of the digital output code than for another bit of the digital output code, wherein the one bit is a more significant bit than the another bit.
6. The method of claim 2 , wherein said selecting comprises adjusting a time constant of an RC circuit to obtain the selected settling time.
7. The method of claim 2 , wherein said selecting comprises adjusting an effective resistance value of an RC circuit to obtain the selected settling time.
8. The method of claim 2 , wherein said selecting comprises selectively actuating one or more switches to short circuit one or more resistors of an RC circuit to obtain the selected settling time.
9. The method of claim 2 , wherein said selecting comprises adjusting an effective capacitance value of an RC circuit to obtain the selected settling time.
10. The method of claim 2 , wherein said selecting comprises selectively opening one or more switches to effectively remove one or more capacitors from an RC circuit to obtain the selected settling time.
11. The method of claim 2 , further comprising:
providing the digital-to-analog converter with a digital reference code that corresponds to an approximation of the analog input value; and
generating the analog reference value with the digital-to-analog converter based upon the digital reference code.
12. The method of claim 2 , wherein said comparator settling time is uniform for each bit position of the digital output code.
13. The method of claim 1 , wherein the analog input value corresponds to a differential analog input value.
14. An apparatus, comprising:
a digital-to-analog converter configured to generate an analog reference value based on a received digital reference value;
a comparator configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value; and
control logic circuitry configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
15. The apparatus of claim 14 , further comprising:
a digital-to-analog timer configured to specify the allotted settling time for the digital-to-analog converter;
wherein the control logic circuitry is further configured to adjust the digital-to-analog timer for the allotted settling time.
16. The apparatus of claim 15 , wherein the control logic circuitry is further configured to allot a greater settling time for a most significant bit of the digital output code than for a least significant bit of the digital output code.
17. The apparatus of claim 15 , wherein the control logic circuitry is further configured to allot a greater settling time for a most significant bit of the digital output code than for a second most significant bit of the digital output code.
18. The apparatus of claim 15 , wherein the control logic circuitry is further configured to allot a greater settling time for one bit of the digital output code than for another bit of the digital output code, wherein the one bit is a more significant bit than the another bit.
19. The apparatus of claim 15 , wherein:
the digital-to-analog timer comprises an RC circuit; and
the control logic circuitry is further configured to adjust a time constant of the RC circuit to obtain the allotted settling time.
20. The apparatus of claim 15 , wherein:
the digital-to-analog timer comprises an RC circuit; and
the control logic circuitry is further configured to adjust an effective resistance value of the RC circuit to obtain the allotted settling time.
21. The apparatus of claim 15 , wherein:
the digital-to-analog timer comprises one or more switches configured to short circuit one or more resistors of an RC circuit; and
the control logic circuitry is further configure to selectively actuate the one or more switches to short circuit the one or more resistors of the RC circuit to obtain the allotted settling time.
22. The apparatus of claim 15 , wherein:
the digital-to-analog timer comprises an RC circuit; and
the control logic circuitry is further configured to adjust an effective capacitance value of the RC circuit to obtain the allotted settling time.
23. The apparatus of claim 15 , wherein:
the digital-to-analog timer comprises one or more switches; and
the control logic circuitry is further configure to selectively open the one or more switches to effectively remove one or more capacitors from the RC circuit to obtain the allotted settling time.
24. The apparatus of claim 15 , wherein:
the comparator is further configured to sample the analog reference value after expiration of the allotted settling time; and
the control logic circuitry is further configured to update the bit position a comparator settling time after sampling the analog reference value.
25. The apparatus of claim 15 , wherein the control logic circuitry is further configured to update the bit position after expiration of a uniform comparator settling time.