IP Library Granted Patent US 9,391,115
Granted Patent B1
US 9,391,115 · App. 14/740,282 · Granted Jul 12, 2016

CMOS image sensor unit and method for fabricating the same

Inventors: Chih-Ping Chung (Hsinchu, TW); Ming-Wei Chen (Changhua County, TW); Min-Hui Chen (Hsinchu County, TW); Ming-Yu Ho (Taichung, TW)
Assignee: Powerchip Technology Corporation
H01L27/14643H01L27/14612H01L27/14689
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Quick Facts
Patent No.
US 9,391,115
App. No.
14/740,282
Granted
Jul 12, 2016
Kind
B1
Abstract

A CMOS image sensor unit and a method for fabricating the same are described. The image sensor unit includes a photodiode, a transfer gate, a reset gate, a source follower gate, a floating drain region between the transfer gate and the reset gate, and a PIP capacitor. The lower poly-Si electrode of the PIP capacitor is electrically connected with the floating drain region and the source follower gate to also serve as an interconnect between the floating drain region and the source follower gate. The fabrication method includes forming contact plugs on the floating drain region and the source follower gate, and then forming a PIP capacitor whose lower poly-Si electrode is connected with each contact plug.

Claims (26)

1. A CMOS image sensor unit, comprising:

a photodiode, disposed in a semiconductor substrate;

a transfer gate, disposed on the semiconductor substrate next to the photodiode;

a reset gate, disposed on the semiconductor substrate;

a floating drain region, disposed in the semiconductor substrate between the transfer gate and the reset gate;

a source follower gate, disposed on the semiconductor substrate; and

a poly-Si/insulator/poly-Si (PIP) capacitor, having a lower poly-Si electrode electrically connected with the floating drain region and the source follower gate to also serve as an interconnect between the floating drain region and the source follower gate,

wherein the lower poly-Si electrode is electrically connected with the floating drain region and the source follower gate respectively via different poly-Si contact plugs.

2. The CMOS image sensor unit of claim 1 , wherein the semiconductor substrate comprises doped monocrystalline silicon, and the transfer gate, the reset gate and the source follower gate comprises doped poly-Si.

3. The CMOS image sensor unit of claim 1 , wherein the transfer gate is disposed on the semiconductor substrate at a first side of the photodiode, and the source follower gate is disposed on the semiconductor substrate at a second side of the photodiode.

4. The CMOS image sensor unit of claim 1 , further comprising:

a pinning layer, disposed in the semiconductor substrate on the photodiode.

5. A method for fabricating a CMOS image sensor unit, comprising:

providing a semiconductor substrate, wherein a transfer gate, a reset gate and a source follower gate are formed on the semiconductor substrate, a photodiode and a floating drain region are formed in the semiconductor substrate, the transfer gate is disposed next to the photodiode, and the floating drain region is disposed between the transfer gate and the reset gate;

forming a plurality of contact plugs above the floating drain region and the source follower gate; and

forming a poly-Si/insulator/poly-Si (PIP) capacitor having a lower poly-Si electrode electrically connected with the contact plugs to also serve as an interconnect between the floating drain region and the source follower gate,

wherein forming the contact plugs above the floating drain region and the source follower gate and forming the poly-Si/insulator/poly-Si capacitor comprise:

forming an insulating layer on the semiconductor substrate;

forming a plurality of contact openings in the insulating layer above the floating drain region and the source follower gate;

forming a first poly-Si layer filling in the contact openings to form the contact plugs;

forming a dielectric layer on the first poly-Si layer;

forming a second poly-Si layer on the dielectric layer; and

patterning the second poly-Si layer, the dielectric layer and the first poly-Si layer to form the poly-Si/insulator/poly-Si capacitor.

6. The method of claim 5 , wherein the semiconductor substrate comprises doped monocrystalline silicon, and the transfer gate, the reset gate and the source follower gate comprises doped poly-Si.

7. The method of claim 5 , wherein the transfer gate is disposed on the semiconductor substrate at a first side of the photodiode, and the source follower gate is disposed on the semiconductor substrate at a second side of the photodiode.

8. The method of claim 5 , wherein a pinning layer is further formed in the semiconductor substrate on the photodiode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049770/0171 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2015
From: CHUNG, CHIH-PING; CHEN, MING-WEI; CHEN, MIN-HUI; HO, MING-YU
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 035901/0709 →
Priority Claims (1)
TW 104112060 A · Apr 15, 2015 · national