Memory system, memory controller and control device

1. A memory system comprising:

a semiconductor memory;

a memory controller configured to control writing and reading of information to and from the semiconductor memory;

a temperature information receiver configured to receive temperature information, the temperature information receiver being provided in the memory controller;

a gradient determining circuit provided in the memory controller, the gradient determining circuit being configured to:

detect a first timing and a second timing, the first timing being a timing at which the temperature information received by the temperature information receiver exceeds a first threshold, the second timing being a timing at which the temperature information received by the temperature information receiver exceeds a second threshold without the temperature information received by the temperature information receiver being equal to or less than the first threshold, the second threshold being higher than the first threshold;

calculate, from time difference between the first timing and the second timing, steepness of a temperature increase using a counter which starts counting after the temperature information exceeds the first threshold and stops counting when the temperature information reaches the second threshold and resets the counting when the temperature information becomes equal to or less than the first threshold; and

determine a gradient related to the steepness of the temperature increase of at least one of the semiconductor memory and the memory controller; and

a temperature controller configured to perform a control operation to suppress the temperature increase based on a comparison of the gradient determined by the gradient determining circuit with a predetermined temperature gradient.

2. The memory system according to claim 1 , wherein the temperature controller is configured to stop memory control operation performed on the semiconductor memory, in case the gradient determined by the gradient determining circuit is greater than or equal to the predetermined temperature gradient.

3. The memory system according to claim 1 , wherein the temperature controller is configured to suppress, in case the gradient determined by the gradient determining circuit is less than or equal to the predetermined temperature gradient, the number of parallel processes performed during parallel control in which the memory controller divides transferred information into pieces of information and writes the pieces of divided information to a plurality of chips of the semiconductor memory simultaneously.

4. The memory system according to claim 1 , wherein the temperature controller is configured to switch parallel control to normal control, in case the gradient determined by the gradient determining circuit is less than or equal to the predetermined temperature gradient, the parallel control indicating control in which the memory controller divides transferred information into pieces of information and simultaneously writes the pieces of divided information to a plurality of chips of the semiconductor memory, the normal control indicating control in which the memory controller, after completing writing of transferred information to one chip of the semiconductor memory, writing to another chip starts.

5. The memory system according to claim 1 , wherein the temperature controller is configured to notify a control device of the gradient determined by the gradient determining circuit, and allow the control device to perform a process of suppressing the temperature increase based on a result of the gradient determination, the control device performing overall control of an entire device where the memory system is mounted.

6. The memory system according to claim 1 , wherein the temperature controller is configured to evacuate information stored in the semiconductor memory to a nonvolatile area, according to the gradient determined by the gradient determining circuit.

7. The memory system according to claim 1 , further comprising a temperature measuring circuit configured to measure an ambient temperature of at least one of the semiconductor memory and the memory controller,

wherein the temperature information receiver receives the temperature information about a plurality of temperatures measured by the temperature measuring circuit.

8. The memory system according to claim 7 ,

wherein the semiconductor memory is mounted on a first surface of a substrate and the memory controller is mounted on a second surface of the substrate, and

wherein the temperature measuring circuit is provided on both of the surfaces of the substrate.

9. The memory system according to claim 7 ,

wherein the semiconductor memory and the memory controller are mounted on one surface of a substrate, and

wherein the temperature measuring circuit is provided within the memory controller.

10. The memory system according to claim 1 , wherein the temperature information receiver receives the temperature information about a plurality of temperatures measured by a temperature sensor communicatively coupled to the system.

11. A memory controller comprising:

a controller configured to control a program of writing information to a semiconductor memory;

a temperature information receiver configured to receive ambient temperature information of the semiconductor memory;

a gradient determining circuit configured to:

detect a first timing and a second timing, the first timing being a timing at which the temperature information received by the temperature information receiver exceeds a first threshold, the second timing being a timing at which the temperature information received by the temperature information receiver exceeds a second threshold without the temperature information received by the temperature information receiver being equal to or less than the first threshold, the second threshold being higher than the first threshold;

calculate, from time difference between the first timing and the second timing, steepness of a temperature increase using a counter which starts counting after the temperature information exceeds the first threshold and stops counting when the temperature information reaches the second threshold and resets the counting when the temperature information becomes equal to or less than the first threshold; and

determine a gradient related to the steepness of the temperature increase of the semiconductor memory; and

a temperature controller configured to perform a control operation to suppress the temperature increase based on the comparison of the gradient determined by the gradient determining circuit with a predetermined temperature gradient.

12. The memory controller according to claim 11 , wherein the temperature controller is configured to stop memory control operation performed on the semiconductor memory, in case the gradient determined by the gradient determining circuit is greater than or equal to the predetermined temperature gradient.

13. The memory controller according to claim 11 , wherein the temperature controller is configured to suppress, in case the gradient determined by the gradient determining circuit is less than or equal to the predetermined temperature gradient, the number of parallel processes performed during parallel control in which the memory controller divides transferred information into pieces of information and writes the pieces of divided information to a plurality of chips of the semiconductor memory simultaneously.

14. The memory controller according to claim 11 , wherein the temperature controller is configured to switch parallel control to normal control in case the gradient determined by the gradient determining circuit is less than or equal to the predetermined temperature gradient, the parallel control indicating control in which the memory controller divides transferred information into pieces of information and simultaneously writes the pieces of divided information to a plurality of chips of the semiconductor memory, the normal control indicating control in which the memory controller, after completing writing of transferred information to one chip of the semiconductor memory, writing to another chip starts.

15. The memory controller according to claim 11 , wherein the temperature controller is configured to notify a control device of the gradient determined by the gradient determining circuit, and allow the control device to perform a process of suppressing the temperature increase based on a result of the gradient determination, the control device performing overall control of an entire device where the memory controller is mounted.

16. The memory controller according to claim 11 , wherein the temperature controller is configured to evacuate information stored in the semiconductor memory to a nonvolatile area, according to the gradient determined by the gradient determining circuit.

17. The memory controller according to claim 11 , further comprising a temperature measuring circuit configured to measure an ambient temperature of the memory controller and the semiconductor memory,

wherein the temperature information receiver receives the temperature information about a plurality of temperatures measured by the temperature measuring circuit.

18. The memory controller according to claim 11 , wherein the temperature information receiver receives the temperature information about a plurality of temperatures measured by a temperature sensor communicatively coupled to the memory controller.

19. A control device comprising:

a receiver configured to receive a gradient from a memory controller, the memory controller being configured to:

control writing and reading of information to and from a semiconductor memory;

detect a first timing and a second timing, the first timing being a timing at which the temperature information received by the temperature information receiver exceeds a first threshold, the second timing being a timing at which the temperature information received by the temperature information receiver exceeds a second threshold without the temperature information received by the temperature information receiver being equal to or less than the first threshold, the second threshold being higher than the first threshold;

calculate, from time difference between the first timing and the second timing, steepness of a temperature increase using a counter which starts counting after the temperature information exceeds the first threshold and stops counting when the temperature information reaches the second threshold and resets the counting when the temperature information becomes equal to or less than the first threshold; and

determine a gradient related to the steepness of the temperature increase of at least one of the semiconductor memory and the memory controller; and

a temperature processor configured to allow the semiconductor memory and the memory controller to perform a process of protecting various types of information stored in the semiconductor memory from being corrupted due to the temperature increase, based on the comparison of the determined gradient received by the receiver with a predetermined temperature gradient.

20. The control device according to claim 19 , wherein the temperature processor suppresses access to the semiconductor memory, based on the gradient.