Use disposable gate cap to form transistors, and split gate charge trapping memory cells
View Patent ↗A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
1. A method of fabricating a semiconductor device having a first, second, and third region on a substrate, comprising:
disposing a first gate layer over a first dielectric on the substrate;
disposing a cap layer over the first gate layer;
forming a plurality of memory cells in the first region, comprising,
etching through the cap layer and the first gate layer in the first region to define at least one select gate disposed over the first dielectric,
disposing a second dielectric over the at least one select gate and the substrate in at least the first region,
disposing a second gate layer over the second dielectric,
etching the second gate layer to define at least one memory gate disposed over the second dielectric, each of the at least one memory gates adjacent to a corresponding sidewall of one of the at least one select gates, and
forming a first doped region in the substrate adjacent to one side of the at least one select gate and a second doped region in the substrate adjacent to an opposite side of the memory gate adjacent to the at least one select gate;
etching through the cap layer and the first gate layer in the second region to define a first transistor gate having an initial thickness substantially equal to a thickness of the cap layer and the first gate layer;
forming a third doped region in the substrate adjacent to the first transistor gate;
removing the cap layer;
etching through the first gate layer in the third region to define a second transistor gate having a thickness substantially equal to the thickness of the first gate layer; and
forming a fourth doped region in the substrate adjacent to the second transistor gate, wherein the third doped region extends deeper in the substrate than the fourth doped region, and wherein a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
2. The method of claim 1 , wherein disposing the second dielectric comprises disposing one or more dielectric layers by sequentially disposing oxide, nitride, and oxide (ONO) layers.
3. The method of claim 1 , wherein etching the second gate layer comprises performing an etch-back process to define the memory gate that is self-aligned adjacent to the sidewall of the select gate.
4. The method of claim 1 , further comprising forming the first dielectric on the substrate before disposing the first gate layer, wherein the first dielectric has a first thickness in the second region associated with the first transistor gate and a second thickness in the third region associated with the second transistor gate.
5. The method of claim 1 , wherein disposing a cap layer comprises disposing a silicon nitride layer.
6. The method of claim 1 , wherein disposing a cap layer comprises disposing one or more layers of silicon nitride or silicon dioxide.
7. The method of claim 1 , further comprising forming silicide over at least a top surface of the first transistor gate, the second transistor gate, the at least one select gate, and the at least one memory gate.
8. A method of fabricating a semiconductor device having a first, second, and third region on a substrate, comprising:
disposing a first dielectric on the substrate;
disposing a first gate layer over the first dielectric;
disposing a cap layer over the first gate layer;
forming a plurality of memory cells in the first region, comprising:
etching through the cap layer and the first gate layer in the first region to define at least one select gate disposed over the first dielectric,
disposing a second dielectric over the at least one select gate and the substrate in at least the first region,
disposing a second gate layer over the second dielectric,
etching the second gate layer to define at least one memory gate disposed over the second dielectric, each of the at least one memory gates adjacent to a corresponding sidewall of one of the at least one select gates, and
forming a first doped region in the substrate adjacent to one side of the at least one select gate and a second doped region in the substrate adjacent to an opposite side of the memory gate adjacent to the at least one select gate;
etching through the cap layer and the first gate layer in the second region to define a first transistor gate having an initial thickness substantially equal to a thickness of the cap layer and the first gate layer;
forming a third doped region in the substrate adjacent to the first transistor gate;
removing the cap layer;
etching through the first gate layer in the third region to define a second transistor gate having a thickness substantially equal to the thickness of the first gate layer; and
forming a fourth doped region in the substrate adjacent to the second transistor gate, wherein the third doped region extends deeper in the substrate than the fourth doped region, and wherein a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
9. The method of claim 8 , wherein disposing the first dielectric comprises sequentially disposing oxide, nitride, and oxide (ONO) layers.
10. The method of claim 8 , wherein etching the second gate layer comprises performing an etch-back process to define the select gate that is self-aligned adjacent to the sidewall of the memory gate.