Superconducting digital phase rotator
An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.
1. A digital phase adjustment circuit, comprising:
an input port configured to receive an input signal;
a pair of ports comprising an advance phase input port configured to receive an advance phase input signal and a retard phase input port configured to receive a retard phase input signal;
a logical device, configured to:
receive the input signal, the advance phase input signal, and the retard phase input signal,
decimate the input signal to produce a decimated representation of the input signal; and
produce an output corresponding to a signal selected from the group consisting of:
the decimated representation of the input signal, having at least one pulse inserted into the decimated input signal responsive to a magnitude of the advance phase input signal, and
the decimated representation of the input signal, having at least one pulse suppressed from the decimated input signal responsive to a magnitude of the retard phase input signal;
wherein at least one of the advance phase input signal and the retard phase input signal has at least three states, and the logical device is configured to respectively insert or suppress a variable number of pulses per period of the decimated representation of the input signal dependent on the at least three states; and
an output port configured to present the output corresponding to the signal produced by the logical device.
2. The digital phase adjustment circuit of claim 1 , wherein the input signal comprises a multi-GHz signal, and the output comprises a communication signal phase modulated responsive to the advance phase input signal and the retard phase input signal.
3. The digital phase adjustment circuit of claim 2 , further comprising a synchronizer circuit configured to synchronize the advance phase input signal and the retard phase input signal with the input signal to reduce phase error in the multi-GHz signal.
4. The digital phase adjustment circuit of claim 2 , wherein the input signal has a frequency of greater than about 16 GHz.
5. The digital phase adjustment circuit of claim 1 , wherein the logical device is configured to produce the output corresponding to a signal representing an increase in a frequency of the decimated representation of the input signal in response to the advance phase input signal, and representing a decrease in a frequency of the decimated representation of the input signal in response to the retard phase input signal.
6. The digital phase adjustment circuit of claim 1 , wherein the input signal comprises a digitally modulated pulse train.
7. The digital phase adjustment circuit of claim 1 , wherein the advance phase input signal and the retard phase input signal are dependent on an analog signal received at an analog input port.
8. The digital phase adjustment circuit of claim 1 , further comprising an analog filter configured to filter the output from the output port, to generate an analog output signal representing a digitally synthesized analog signal, wherein the input signal is a multi-GHz signal.
9. The digital phase adjustment circuit of claim 1 , wherein the logical device comprises at least two Josephson junctions on an integrated circuit.
10. The digital phase adjustment circuit of claim 1 , wherein at least one of the advance phase input signal and the retard phase input signal comprises a multi-bit digital signal, wherein a number of pulses inserted or suppressed is dependent on a digital magnitude of the multi-bit digital signal.
11. The digital phase adjustment circuit of claim 10 , wherein the multi-bit digital signal comprises a plurality of concurrently presented equal-weighted bits.
12. The digital phase adjustment circuit of claim 10 , wherein the multi-bit digital signal comprises a plurality of binary-weighted bits.
13. A digital phase adjustment method, comprising:
receiving an input pulse signal through an input port;
receiving an advance phase input pulse signal and a retard phase input pulse signal; and
producing an output corresponding to a decimated input pulse signal, having at least one pulse inserted into the decimated input pulse signal selectively responsive to the advance phase input pulse signal, and having at least one pulse suppressed from the decimated input pulse signal responsive to the retard phase input pulse signal,
wherein at least one of the advance phase input pulse signal and the retard phase input pulse signal has a range comprising at least three states, and in response to at least one of the at least three states, a plurality of respective pulses are inserted or suppressed per period of the decimated input pulse signal.
14. The method of claim 13 , wherein the input signal comprises a multi-GHz signal, and the output comprises a communication signal phase modulated responsive to the advance phase input signal and a retard phase input signal.
15. The method of claim 13 , wherein the input signal comprises a multi-GHz signal, the advance phase input pulse signal and the retard phase input pulse signal are derived from an analog signal, wherein the output comprises a digitized signal phase modulated responsive to the analog signal.
16. The method of claim 13 , further comprising synchronizing the advance phase input pulse signal and the retard phase input pulse signal with the input pulse signal to reduce phase error in the output.
17. The method of claim 13 , wherein the output is produced by a logical device comprising an integrated circuit having at least two Josephson junctions.
18. The method of claim 13 , wherein at least one of the advance phase input pulse signal and the retard phase input pulse signal comprises a multi-bit digital pulse signal, wherein a number of pulses inserted or suppressed in the output is dependent on a digital magnitude of the multi-bit digital pulse signal.
19. A digital phase adjustment apparatus, comprising:
a signal input port configured to receive an input signal;
a phase adjust input port configured to receive a phase advance signal and a phase retard signal;
a logical device, configured to receive the input signal, a clock input, the phase advance signal and the phase retard signal, and to produce an output signal corresponding to a decimated representation of the input signal, at a digital data rate corresponding to the clock input decimated by a decimation factor and having at least one pulse inserted responsive to the phase advance signal, and at least one pulse suppressed responsive to the phase retard signal; and
an output port configured to present the output signal,
wherein at least one of the phase advance signal and the phase retard signal comprises a multi-bit digital signal, wherein a number of pulses inserted or suppressed per period of the clock input decimated by the decimation factor is dependent on a respective state of the multi-bit digital signal.
20. The digital phase adjustment circuit according to claim 19 , wherein the input signal comprises a multi-GHz signal, and the output comprises a communication signal phase modulated responsive to the phase advance signal and the phase retard signal.