INTEGRATED ESD PROTECTION CIRCUITS IN GAN
An electronic circuit is disclosed and described herein. The circuit includes first and second pins, and an overvoltage protection circuit including a first enhancement-mode transistor. The overvoltage protection circuit is disposed on a GaN-based substrate, and the first enhancement mode transistor is configured to provide overvoltage protection between the first and second pins.
1 . A circuit, comprising:
first and second pins; and
an overvoltage protection circuit comprising a first enhancement-mode transistor, wherein the overvoltage protection circuit is disposed on a GaN-based substrate,
wherein the first enhancement mode transistor is configured to provide overvoltage protection between the first and second pins.
2 . The circuit of claim 1 , wherein the overvoltage protection circuit does not contain depletion-mode transistors.
3 . The circuit of claim 1 , wherein the overvoltage protection circuit comprises at least one diode-connected transistor disposed between the first and second pins.
4 . The circuit of claim 1 , wherein the overvoltage protection circuit comprises:
second and third enhancement-mode transistors, wherein a source of the second enhancement-mode transistor is coupled to a gate of the third enhancement-mode transistor; and
an electrically conductive element coupled in an electrical path between the source of the second enhancement-mode transistor and a source of the first enhancement-mode transistor, wherein the electrically conductive element comprises at least one of: a resistor, a depletion-mode transistor, a reference current sink, and a reference current source.
5 . The circuit of claim 1 , wherein the overvoltage protection circuit comprises:
second and third enhancement-mode transistors, wherein a source of the second enhancement-mode transistor is coupled to a gate of the third enhancement-mode transistor; and
an electrically conductive element coupled in an electrical path between the source of the second enhancement-mode transistor and the gate of the third enhancement-mode transistor, wherein the electrically conductive element comprises at least one of: a resistor, a depletion-mode transistor, a reference current sink, and a reference current source.
6 . The circuit of claim 1 , wherein the overvoltage protection circuit is configured to remain in an off state until a voltage potential across the first and the second pins is above a threshold voltage level.
7 . The circuit of claim 1 , wherein one or more diodes or diode-connected transistors are connected in series and coupled between a drain of the first enhancement-mode transistor and a gate of the first enhancement-mode transistor.
8 . The circuit of claim 7 , wherein an electrically conductive element is coupled in an electrical path between the gate of the first enhancement-mode transistor and a source of the first enhancement-mode transistor, wherein the electrically conductive element comprises at least one of: a resistor, a depletion-mode transistor, a reference current sink, and a reference current source.
9 . The circuit of claim 1 , wherein the first enhancement-mode transistor is configured to conduct a current of at least 500 mA when exposed to an overvoltage pulse.
10 . The circuit of claim 1 , wherein the overvoltage protection circuit comprises second and third enhancement-mode transistors, wherein a source of the third enhancement-mode transistor is connected to a gate of the second enhancement-mode transistor, and wherein a source of the second enhancement-mode transistor is connected to a gate of the first enhancement-mode transistor.
11 . The circuit of claim 1 , wherein, in response to a changing voltage between the first and second pins changing with a rate greater than 1V/ns, the first enhancement-mode transistor is configured to turn on so as to conduct current between the first and second pins.
12 . The circuit of claim 11 , further comprising a dv/dt detection filter connected between a drain of the first enhancement-mode transistor and a source of the first enhancement-mode transistor, wherein the dv/dt filter is configured to power a gate of the first enhancement-mode transistor in response to the changing voltage.
13 . The circuit of claim 12 , further comprising a GaN-based logic circuit connected to the dv/dt filter and coupled to a gate of the first enhancement-mode transistor, wherein the logic circuit comprises at least one of: an inverter and a buffer.
14 . The circuit of claim 13 , wherein the logic circuit is configured to maintain the first enhancement mode in a conductive state for at least the total duration of a rise and a fall of the changing voltage.
15 . The circuit of claim 11 , further comprising a second enhancement mode transistor, wherein a source of the second enhancement mode transistor is connected to a source of the first enhancement mode transistor, and wherein a drain of the second enhancement mode transistor is connected to a gate of the first enhancement mode transistor.
16 . The circuit of claim 15 , further comprising a dv/dt detection filter connected between a drain of the first enhancement-mode transistor and a source of the first enhancement-mode transistor, wherein the dv/dt filter is configured to power a gate of the second enhancement-mode transistor in response to the changing voltage changing with a rate less than 1V/ns.
17 . The circuit of claim 16 , further comprising a GaN-based logic circuit connected to the dv/dt filter and coupled to a gate of the second enhancement-mode transistor, wherein the logic circuit comprises at least one of: an inverter and buffer.
18 . The circuit of claim 11 , wherein a drain of the first enhancement-mode transistor is connected to the first pin and a source of the first enhancement-mode transistor is connected to the second pin.
19 . The circuit of claim 11 , wherein a current limiting element is disposed between the first pin and a drain of the first enhancement-mode transistor, wherein the current limiting element comprises at least one of: a resistor, a depletion mode transistor, and a current source, and wherein a source of the first enhancement-mode transistor is connected to the second pin.
20 . The circuit of claim 18 , wherein the current limiting element is configured to limit the current flowing therethrough in response to a voltage thereacross exceeding 10V.
21 . The circuit of claim 1 , wherein the first pin is connected to the gate of a power transistor and the second pin is connected to the source of the power transistor.
22 . The circuit of claim 1 , wherein the first pin is connected to a power supply terminal and the second pin is connected to the source of a power transistor.
23 . The circuit of claim 1 , wherein the first pin connected to is an input to a logic circuit and the second pin is connected to one of: a power supply terminal, and the source of a power transistor.
24 . The circuit of claim 1 , wherein the first pin is connected to a first power supply terminal and the second pin is connected to a second power supply terminal.
25 . An electronic power conversion component comprising:
a package base; and
one or more GaN-based dies secured to the package base, wherein the GaN-based die comprises:
a first circuit comprising at least one enhancement-mode transistor; and
an overvoltage protection circuit coupled to the first circuit.
26 . A method of operating a GaN-based circuit, the method comprising:
receiving a voltage greater than a threshold across two pins of the circuit; and
in response to the received voltage, turning on a GaN-based enhancement-mode transistor coupled between the two pins, such that the enhancement-mode transistor conducts current between the two pins while the voltage potential is greater than the threshold.
27 . The method of claim 26 , further comprising:
receiving a changing voltage between the two pins changing with a rate greater than 1V/ns; and
in response to the changing voltage, turning on the first enhancement-mode transistor so as to conduct current between the two pins.