Controller, semiconductor memory system and operating method thereof

1. An operating method of a controller, comprising:

when a first ECC decoding on data read from a semiconductor memory device according to a hard read voltage fails, generating one or more quantization intervals based on a number of unsatisfied syndrome check (USC), which is a result of the first ECC decoding; and

performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals.

2. The operating method of claim 1 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

3. The operating method of the controller of claim 2 , wherein the USC is a nonzero element of a vector generated by a syndrome check of the LDPC decoding.

4. The operating method of claim 3 , wherein the first ECC decoding comprises:

performing the LDPC decoding by reading the data from the semiconductor memory device according to the hard read voltage; and

determining whether the first ECC decoding is successful based on the USC included in the vector generated by the syndrome check.

5. The operating method of claim 1 , wherein the quantization intervals are generated based on the number of USC according to following equation,

Δ i =a ×USC V1 +b [step]  [Equation]

wherein “Δ i ” represents one of the quantization intervals, “i” represents an index for the quantization intervals, “USC V1 ” represents the number of USC, and “a” and “b” are coefficient values that are obtained through a heuristic approach or from characteristics of the semiconductor memory device.

6. The operating method of claim 5 , wherein the quantization intervals are generated based on a quantization interval table having the number of USC as its index and preset by the Equation.

7. The operating method of claim 1 , wherein the second ECC decoding is performed on the data read from the semiconductor memory device in response to the soft read voltages, each of which is spaced apart in voltage level from the hard read voltage by a corresponding one of the quantization intervals.

8. The operating method of claim 7 , wherein the second ECC decoding is performed on the data read from the semiconductor memory device according to each of the soft read voltages until the second ECC decoding is successful.

9. The operating method of claim 1 ,

wherein the first ECC decoding is a hard decision decoding, and

wherein the second ECC decoding is a soft decision decoding.

10. A controller comprising:

a quantization interval generation unit for generating one or more quantization intervals based on a number of unsatisfied syndrome check (USC), which is a result of a first ECC decoding on data read from a semiconductor memory device according to a hard read voltage, when the first ECC decoding fails; and

an ECC unit for performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals.

11. The controller of claim 10 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

12. The controller of claim 11 , wherein the USC is a nonzero element of a vector generated by a syndrome check of the LDPC decoding.

13. The controller of claim 12 , wherein:

the LDPC decoding is performed by reading the data from the semiconductor memory device according to the hard read voltage; and

whether the first ECC decoding is successful is determined based on the USC included in the vector generated by the syndrome check.

14. The controller of claim 10 , wherein the quantization interval generation unit for generating the quantization intervals generates the quantization intervals based on the number of USC according to following equation,

Δ i =a ×USC V1 +b [step]  [Equation]

wherein “Δ i ” represents one of the quantization intervals, “i” represents index for the quantization intervals, “USC V1 ” represents the number of USC, and “a” and “b” are coefficient values that are obtained through a heuristic approach or from characteristics of the semiconductor memory device.

15. The controller of claim 14 , wherein the quantization interval generation unit for generating the quantization intervals generates the quantization intervals based on a quantization interval table having the number of USC as its index and is preset by the Equation.

16. The controller of claim 10 , wherein the ECC unit for performing the second ECC decoding performs the second ECC decoding on the data read from the semiconductor memory device according to the soft read voltages, each of which is spaced apart in voltage level from the hard read voltage by a corresponding one of the quantization intervals.

17. The controller of claim 16 , wherein the ECC unit for performing the second ECC decoding performs the second ECC decoding on the data read from the semiconductor memory device according to each of the soft read voltages until the second ECC decoding is successful.

18. The controller of claim 10 ,

wherein the first ECC decoding is a hard decision decoding, and

wherein the second ECC decoding is a soft decision decoding.

19. A semiconductor memory system comprising:

a semiconductor memory device; and

a controller,

wherein the controller comprises:

a quantization interval generation unit for generating one or more quantization intervals based on a number of unsatisfied syndrome check (USC), which is a result of a first ECC decoding on data read from the semiconductor memory device according to a hard read voltage, when the first ECC decoding fails; and

an ECC unit for performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals.

20. The semiconductor memory system of claim 19 , wherein the USC is a nonzero element of a vector generated by a syndrome check of a low density parity check (LDPC) decoding.