IP Library Granted Patent US 9,413,493
Granted Patent B2
US 9,413,493 · App. 14/744,015 · Granted Aug 9, 2016

Apparatus and method for communicating data over a communication channel

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Quick Facts
Patent No.
US 9,413,493
App. No.
14/744,015
Granted
Aug 9, 2016
Kind
B2
Abstract

For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

Claims (60)

1. A modulator comprising:

a symbol mapper for mapping a bit stream into symbols, the bit stream comprising an LSB (Least Significant Bit) sequence and a non-LSB sequence; and

a multi-level encoder comprising a inner encoder and an outer encoder for encoding only the LSB sequence of the bit stream such that an information block size of the inner encoder is identical to field size of the outer encoder;

wherein both the inner encoder and the outer encoder of the multi-level encoder avoid encoding the non-LSB sequence.

2. The modulator of claim 1 , wherein:

the inner encoder is a block encoder; and

the outer encoder is an RS (Reed-Solomon) encoder.

3. The modulator of claim 1 , wherein:

the inner encoder is a Hamming or Extended Hamming encoder; and

the outer encoder is an RS (Reed-Solomon) encoder.

4. The modulator of claim 1 , wherein:

the inner encoder is a single-parity-check encoder; and

the outer encoder is an RS (Reed-Solomon) encoder.

5. The modulator of claim 1 , further comprising:

a second encoder for encoding the non-LSB sequence of the bit stream.

6. The modulator of claim 5 , wherein the second encoder is an RS (Reed-Solomon) encoder.

7. The modulator of claim 1 , wherein the symbol mapper performs the mapping without the non-LSB sequence of the bit stream being encoded.

8. The modulator of claim 1 , wherein the field size of the outer encoder is at least 9.

9. A method for modulating a bit stream into symbols, the bit stream comprising an LSB (Least Significant Bit) sequence and a non-LSB sequence, the method comprising:

encoding, by a multi-level encoder comprising an inner encoder and an outer encoder, only the LSB sequence of the bit stream such that an information block size of the inner encoder is identical to a field size of the outer encoder; and

mapping the bit stream into symbols;

wherein both the inner encoder and the outer encoder of the multi-level encoder avoid encoding the non-LSB sequence.

10. The method of claim 9 , further comprising:

encoding, by a second encoder, the non-LSB sequence of the bit stream.

11. A demodulator comprising:

a symbol demapper for demapping symbols into a bit stream, the bit stream comprising an LSB (Least Significant Bit) sequence and a non-LSB sequence; and

a multi-level decoder comprising an inner decoder and an outer decoder for decoding only the LSB sequence of the bit stream such that an information block size of the inner decoder is identical to a field size of the outer decoder;

wherein both the inner decoder and the outer decoder of the multi-level decoder avoid decoding the non-LSB sequence.

12. A demodulator comprising:

a symbol demapper for demapping symbols into a bit stream; and

a multi-level decoder comprising an inner decoder and an outer decoder for decoding only a portion of the bit stream such that an information block size of the inner decoder matches a field size of the outer decoder;

wherein:

the bit stream further comprises a non-LSB sequence having (N−1)-times as many bits as the LSB sequence; and

the symbol demapper is configured for demapping the symbols from a constellation of 2 N -PAM symbols into the bit stream, where N is an integer and is constant from symbol to symbol.

13. A demodulator comprising:

a symbol demapper for demapping symbols into a bit stream; and

a multi-level decoder comprising an inner decoder and an outer decoder for decoding only a portion of the bit stream such that an information block size of the inner decoder matches a field size of the outer decoder;

wherein:

the bit stream further comprises a non-LSB sequence having p-times as many bits as the LSB sequence, where p is an average number of bits per LSB; and

the symbol demapper is configured for demapping the symbols from a constellation of 2 N -PAM symbols into the bit stream, where N is an integer and is variable from symbol to symbol.

14. The demodulator of claim 11 , wherein:

the inner decoder is a block decoder; and

the outer decoder is an RS (Reed-Solomon) decoder.

15. The demodulator of claim 11 , wherein:

the inner decoder is a Hamming or Extended Hamming decoder; and

the outer decoder is an RS (Reed-Solomon) decoder.

16. The demodulator of claim 11 , wherein:

the inner decoder is a single-parity-check decoder; and

the outer decoder is an RS (Reed-Solomon) decoder.

17. The demodulator of claim 11 , further comprising:

a second decoder for decoding the non-LSB sequence of the bit stream.

18. The demodulator of claim 17 , wherein the second decoder is an RS (Reed-Solomon) decoder.

19. The demodulator of claim 11 , wherein the non-LSB sequence of the it stream from the symbol demapper is not decoded.

20. The demodulator of claim 11 , wherein the field size of the outer decoder is at least 9.

21. A method for demodulating symbols into a bit stream, the bit stream comprising an LSB (Least Significant Bit) sequence and a non-LSB sequence, the method comprising:

demapping symbols into the bit stream; and

decoding, by a multi-level decoder comprising an inner decoder and an outer decoder, only the LSB sequence of the bit stream such that an information block size of the inner decoder is identical to a field size of the outer decoder;

wherein both the inner decoder and the outer decoder of the multi-level decoder avoid decoding the non-LSB sequence.

22. The method of claim 21 , further comprising:

decoding, by a second decoder, a non-LSB sequence of the bit stream.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2017
From: CORTINA SYSTEMS, INC.
To: INPHI CORPORATION
Reel/Frame 041363/0402 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2015
From: SMITH, BENJAMIN; FARHOODFAR, ARASH; CROZIER, STEWART; KSCHISCHANG, FRANK R
To: CORTINA SYSTEMS, INC.
Reel/Frame 035965/0350 →