CMOS image sensor

1. A CMOS image sensor comprising:

an image array including M rows and N columns of pixels and N output conductive tracks corresponding respectively to the N columns, where for each column, the pixels of the column are connected to the corresponding output conductive track, and the pixels of different columns are connected to different output conductive tracks, each pixel including a photodiode, a sense node, a transfer transistor coupling the sense node to a first node of the photodiode, a reset transistor coupling the sense node to a pixel reset voltage node, and a read circuit coupling the sense node to the output conductive track corresponding to the column that includes the pixel; and

a test circuit including a first assembly of N elementary reference cells respectively coupled to the N output conductive tracks, each elementary reference cell including a resistor, a sense node, a transfer transistor coupling the sense node of the elementary reference cell to a first node of the resistor, a reset transistor coupling the sense node of the elementary reference cell to a cell reset voltage node, and a read circuit coupling the sense node of the elementary reference cell to the output track to which the elementary reference cell is coupled, the resistors of said first assembly being series-coupled between first and second reference voltage nodes.

2. The sensor of claim 1 , comprising an output stage coupled to said output conductive tracks.

3. The sensor of claim 1 , wherein:

in each pixel, the read circuit of the pixel comprises an amplification transistor assembled as a source follower, having a gate coupled to the sense node of the pixel, and a selection transistor coupling a source of the amplification transistor to the output conductive track corresponding to the column that includes the pixel, and

in each elementary reference cell, the read circuit of the cell comprises an amplification transistor assembled as a source follower, having a gate coupled to the sense node of the cell, and a selection transistor coupling a source of the amplification transistor to the output conductive track to which the cell is coupled.

4. The sensor of claim 1 , wherein each row includes a first control line coupled to respective control nodes of the pixels of the row, and wherein the test circuit includes a first row that includes the elementary reference cells of the first assembly and a second control line coupled to respective control nodes of the elementary reference cells.

5. The sensor of claim 4 , comprising a control circuit configured to successively implement:

resetting the sense node of each pixel in a selected row of the rows of the image array by turning on the reset transistors of the pixels of the selected row;

reading a voltage of the sense node of each pixel in the selected row;

turning on the transfer transistor of each pixel in the selected row; and

reading the voltage of the sense node of each pixel in the selected row.

6. The sensor of claim 5 , wherein said control circuit is further configured to successively implement:

turning on the transfer transistor of each cell in the row of the test circuit;

reading a voltage of the sense node of each cell in the row of the test circuit;

resetting the sense node of each cell in the row of the test circuit by turning on the reset transistor of each cell; and

reading the voltage of the sense node of each cell in the row of the test circuit.

7. The sensor of claim 1 , wherein the test circuit comprises a second assembly of N elementary reference cells respectively coupled to the N output conductive tracks of the sensor, each elementary reference cell of the second assembly including a resistor, a sense node, a transfer transistor coupling the sense node of the elementary reference cell to a first node of the resistor of the elementary reference cell, a reset transistor coupling the sense node of the elementary reference cell to a reset voltage node, and a read circuit coupling the sense node of the elementary reference cell to the output track to which the elementary reference cell is coupled, the resistors of said second assembly being series-coupled between the first and second reference voltage nodes.

8. The sensor of claim 7 , wherein:

the resistor of the reference cell of the first assembly coupled to the conductive track corresponding to the first column of the image array is connected to the first reference voltage node;

the resistor of the reference cell of the first assembly coupled to the conductive track corresponding to the last column of the image array is connected to the second reference voltage node;

the resistor of the reference cell of the second assembly coupled to the conductive track corresponding to the first column of the sensor image array is connected to the second reference voltage node; and

the resistor of the reference cell of the second assembly coupled to the conductive track corresponding to the last column of the image array is connected to the first reference voltage node.

9. The sensor of claim 7 , wherein the test circuit includes a second row that includes the cells of the second assembly and a third control line coupled to respective control nodes of the elementary reference cells of the second assembly.

10. The sensor of claim 7 , wherein the cells of the first assembly and the cells of the second assembly are alternately arranged along a first row of simultaneously-controllable elementary reference cells and along a second row of simultaneously-controllable elementary reference cells.

11. A method of operating a CMOS image sensor, the method comprising:

resetting plural sense nodes of plural pixels, respectively, in a selected row an image array that includes M rows and N columns of pixels and N output conductive tracks corresponding respectively to the N columns, where for each column, the pixels of the column are connected to the corresponding output conductive track, and the pixels of different columns are connected to different output conductive tracks, each pixel including a photodiode, a sense node, a transfer transistor coupling the sense node to a first node of the photodiode, a reset transistor coupling the sense node to a pixel reset voltage node, and a read circuit coupling the sense node to the output conductive track corresponding to the column that includes the pixel, the resetting including turning on the reset transistors of the pixels of the selected row;

reading a voltage of the sense node of each pixel in the selected row;

turning on the transfer transistor of each pixel in the selected row;

reading the voltage of the sense node of each pixel in the selected row;

turning on transfer transistors of cells, respectively, in a row of a test circuit that includes a first assembly of N elementary reference cells respectively coupled to the N output conductive tracks, each elementary reference cell including a resistor, a sense node, a transfer transistor coupling the sense node of the elementary reference cell to a first node of the resistor, a reset transistor coupling the sense node of the elementary reference cell to a cell reset voltage node, and a read circuit coupling the sense node of the elementary reference cell to the output track to which the elementary reference cell is coupled, the resistors of said first assembly being series-coupled between first and second reference voltage nodes;

reading a voltage of the sense node of each cell in the row of the test circuit;

resetting the sense node of each cell in the row of the test circuit by turning on the reset transistor of each cell; and

reading the voltage of the sense node of each cell in the row of the test circuit.

12. The method of claim 11 , wherein:

resetting plural sense nodes occurs before reading the voltage of the sense node of each pixel in the selected row, which occurs before turning on the transfer transistor of each pixel in the selected row, which occurs before reading the voltage of the sense node of each pixel in the selected row; and

turning on the transfer transistors of the cells in the row of the test circuit occurs before reading the voltage of the sense node of each cell in the row of the test circuit, which occurs before resetting the sense node of each cell in the row of the test circuit, which occurs before reading the voltage of the sense node of each cell in the row of the test circuit.

13. The method of claim 11 , comprising reading the cell reset voltages before reading reference voltages of cells.