Via structure for optimizing signal porosity

1. An apparatus including a conductive stack structure, comprising:

a metal x (M x ) layer interconnect on an M x layer and extending in a first direction on a first track;

a metal y (M y ) layer interconnect on an M y layer, the M y layer being a lower layer than the M x layer;

a first via stack coupled between the M x layer interconnect and the M y layer interconnect, the first via stack including a first metal x−1 (M x-1 ) layer interconnect on an M x-1 layer and including a plurality of vias, the first M x-1 layer interconnect being a higher layer than the M y layer interconnect, the first M x-1 layer interconnect extending in a second direction on a second track, the second direction being orthogonal to the first direction, the plurality of vias including a first via connected to the M x layer interconnect and the first M x-1 layer interconnect within an overlapping portion of the first track and the second track, the plurality of vias including a second via coupled between the M y layer interconnect and the first M x-1 layer interconnect, the second via being within an overlapping portion of the first track and the second track;

a second via stack coupled between the M x layer interconnect and the M y layer interconnect, the second via stack including a second M x-1 layer interconnect and a second plurality of vias, the second M x-1 layer interconnect extending in the second direction on a third track, the second plurality of vias including a third via connected to the M x layer interconnect and the second M x-1 layer interconnect within an overlapping portion of the first track and the third track, the second plurality of vias including a fourth via coupled between the M y layer interconnect and the second M x-1 layer interconnect, the fourth via being within an overlapping portion of the first track and the third track;

a second M x layer interconnect extending in the first direction on a fourth track immediately adjacent to the first track; and

a third M x layer interconnect extending in the first direction on a fifth track immediately adjacent to the first track, the M x layer interconnect being between the second M x layer interconnect and the third M x layer interconnect, the second M x layer interconnect and the third M x layer interconnect being uncoupled to each other.

2. The apparatus of claim 1 , wherein:

the first via and the second via each have a width of approximately w, and the first M x-1 layer interconnect extends past the first via and the second via by at least a length 3w; and

the third via and the fourth via each have a width of approximately w, and the second M x-1 layer interconnect extends past the third via and the fourth via by at least a length 3w.

3. The apparatus of claim 1 , further comprising a third M x-1 layer interconnect extending in the second direction between the first M x-1 layer interconnect and the second M x-1 layer interconnect, the third M x-1 layer interconnect being uncoupled to the first M x-1 layer interconnect and the second M x-1 layer interconnect.

4. The apparatus of claim 1 , wherein the M x layer interconnect is uncoupled to any interconnect on the M x layer.

5. The apparatus of claim 1 , wherein the first M x-1 layer interconnect is uncoupled to any interconnect on the M x-1 layer other than the second M x-1 layer interconnect.

6. The apparatus of claim 5 , wherein the first M x-1 layer interconnect is uncoupled to any via between the M x layer and the M x-1 layer except for the first via.

7. The apparatus of claim 1 , wherein the second M x-1 layer interconnect is uncoupled to any interconnect on the M x-1 layer other than the first M x-1 layer interconnect.

8. The apparatus of claim 7 , wherein the second M x-1 layer interconnect is uncoupled to any via between the M x layer and the M x-1 layer except for the third via.

9. The apparatus of claim 1 , wherein the M y layer is an M 3 layer.

10. The apparatus of claim 1 , further comprising a plurality of metal oxide semiconductor (MOS) transistors located below the M y layer interconnect, wherein the M y layer interconnect is coupled to a source of at least one of the plurality of MOS transistors.

11. The apparatus of claim 1 , wherein the first and third vias are separated by at least one track, and the second and fourth vias are separated by at least one track.

12. The apparatus of claim 11 , wherein the first and third vias are separated by one track, and the second and fourth vias are separated by one track.

13. The apparatus of claim 1 , wherein the first M x-1 layer interconnect extends across at least three tracks.

14. The apparatus of claim 1 , wherein the first and second via stacks provide one of power or ground from the M x layer interconnect to the M y layer interconnect.