IP Library Granted Patent US 9,490,362
Granted Patent B2
US 9,490,362 · App. 14/744,890 · Granted Nov 8, 2016

Semiconductor device production method and semiconductor device

Inventors: Fujio Masuoka (Tokyo, JP); Nozomu Harada (Tokyo, JP); Hiroki Nakamura (Tokyo, JP); Yisuo Li (Singapore, SG); Aashit Ramachandra Kamath (Singapore, SG); Zhixian Chen (Singapore, SG); Teng Soong Phua (Singapore, SG); Xinpeng Wang (Singapore, SG); Patrick Guo-Qiang Lo (Singapore, SG)
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
H01L29/7827H01L21/28035H01L21/28238H01L21/28518H01L21/32134H01L21/32139H01L21/823437H01L21/823475H01L21/823487H01L21/823885H01L27/088H01L27/092H01L29/0692H01L29/1037H01L29/1054H01L29/423H01L29/42356H01L29/49H01L29/4916H01L29/66666
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Quick Facts
Patent No.
US 9,490,362
App. No.
14/744,890
Granted
Nov 8, 2016
Kind
B2
Abstract

A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.

Claims (19)

1. A semiconductor device comprising:

a planar semiconductor layer formed on a semiconductor substrate;

first and second pillar-shaped semiconductor layers formed on the planar semiconductor layer;

a first gate insulating film formed around the first pillar-shaped semiconductor layer;

a first gate electrode having a laminated structure constituted by a metal film and a polysilicon film formed around the first gate insulating film;

a second gate insulating film formed around the second pillar-shaped semiconductor layer;

a second gate electrode having a laminated structure constituted by a metal film and a polysilicon film formed around the second gate insulating film;

a gate line connected to the first and second gate electrodes;

an oxide film formed between the gate line and the planar semiconductor layer and having a thickness larger than that of the gate insulating film;

a first n-type diffusion layer formed in an upper portion of the first pillar-shaped semiconductor layer;

a second n-type diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer and an upper portion of the planar semiconductor layer;

a first p-type diffusion layer formed in an upper portion of the second pillar-shaped semiconductor layer; and

a second p-type diffusion layer formed in a lower portion of the second pillar-shaped semiconductor layer and an upper portion of the planar semiconductor layer,

wherein a thickness of the polysilicon film is smaller than a half of a distance between the first pillar-shaped semiconductor layer and the second pillar-shaped semiconductor layer,

a height of an upper surface of the metal film is more than a height of an upper surface of the polysilicon film, and

a height of an upper surface of the gate line is less than a height of upper surfaces of the first and second gate electrodes.

2. The semiconductor device according to claim 1 , wherein the gate line has a laminated structure constituted by the metal film and a silicide.

3. The semiconductor device according to claim 2 , wherein there is a particular offset between a center line of the gate line and a line that connects a center point of the first pillar-shaped semiconductor layer and a center point of the second pillar-shaped semiconductor layer.

4. The semiconductor device according to claim 3 , further comprising silicides formed on the first and second n-type diffusion layers and the first and second p-type diffusion layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2015
From: MASUOKA, FUJIO; HARADA, NOZOMU; NAKAMURA, HIROKI; LI, YISUO; KAMATH, AASHIT R; CHEN, ZHIXIAN; PHUA, TENG S; WANG, XINPENG; LO, PATRICK G
To: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Reel/Frame 035870/0907 →
Continuity (2)
Continuation PCTJP2013061653 · Apr 19, 2013
Related Publication 20150287822A1 · Oct 8, 2015