Fast process flow, on-wafer interconnection and singulation for MEPV
View Patent ↗A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.
1. A method comprising:
providing a substrate comprising a device layer on which a plurality of device cells are defined;
depositing a first dielectric layer on the device layer;
depositing a metal interconnect on the first dielectric layer such that the deposited interconnect is electrically connected to at least two of the device cells and lies across a boundary between at least two of the electrically connected device cells;
depositing a second dielectric layer over the first dielectric layer and over the interconnect; and
exposing at least one contact point on the interconnect through the second dielectric layer.
2. The method of claim 1 , wherein the first dielectric layer comprises a polyimide material.
3. The method of claim 1 , wherein the second dielectric layer comprises one of a polyimide material and a dry film photoresist material.
4. The method of claim 1 , wherein the interconnect formed on the first dielectric layer comprises a thickness of 3 microns or less.
5. The method of claim 1 , wherein:
prior to depositing the metal interconnect on the first dielectric layer, openings are formed in the first dielectric layer to at least two devices belonging to respective ones of the at least two electrically connected device cells; and
forming the interconnect comprises depositing electrically conductive material in the formed openings.
6. The method of claim 5 , wherein forming the interconnect comprises:
depositing an electrically conductive seed layer on a surface of the first dielectric layer;
patterning a masking material with an opening for the interconnect between the openings in the first dielectric layer;
electrodepositing the interconnect material on the seed layer in the opening; and
after electrodepositing the interconnect material, removing the masking material and exposed seed layer.
7. The method of 1 , further comprising forming perforations in the second dielectric layer between the plurality of cells.
8. The method of claim 7 , wherein the perforations comprise rounded edges.
9. The method of claim 1 , wherein the plurality of circuit cells are disposed in an area of the substrate, the method further comprising:
forming perforations in the second dielectric layer at the boundary of the area.
10. The method of claim 9 , wherein the perforations comprise sharp corners.
11. The method of claim 1 , further comprising patterning the second dielectric layer in an area between the at least two electrically connected device cells into a tether around the interconnect.
12. A method comprising:
providing an interconnect to a device of a first circuit cell on a substrate and to a device of a second circuit cell on the substrate;
forming a dielectric layer on the interconnect;
exposing at least one contact point on the interconnect through the dielectric layer; and
forming at least one opening in the dielectric layer between the first circuit cell and the second circuit cell,
wherein the interconnect is electrically connected to the first circuit cell and the second circuit cell, and
wherein the interconnect lies across a boundary between the first circuit cell and the second circuit cell.
13. The method of claim 12 , wherein the opening comprises rounded edges.
14. The method of claim 12 , wherein the first circuit cell and the second circuit cell are ones of a plurality of circuit cells that are disposed in an area of the substrate, the method further comprising:
forming singulation openings in the dielectric layer at the boundary of the area.
15. The method of claim 14 , wherein the singulation openings comprise sharp corners.
16. The method of claim 12 , further comprising patterning the dielectric layer into a tether area around the interconnect material.
17. A method comprising:
providing a device layer, wherein the device layer comprises a plurality of device cells;
depositing a first dielectric layer over the device layer;
depositing a metal interconnect over the first dielectric layer, wherein the metal interconnect is electrically connected to at least two device cells of the plurality of device cells, and wherein the metal interconnect lies across a boundary between at least two device cells of the plurality of device cells;
depositing a second dielectric layer over the metal interconnect; and
exposing at least one contact point on the metal interconnect through the second dielectric layer.
18. The method of claim 17 , wherein the first dielectric layer comprises a polyimide material.
19. The method of claim 17 , wherein the second dielectric layer comprises one of a polyimide material or a dry film photoresist material.
20. The method of claim 17 , wherein the metal interconnect has a thickness of 3 microns or less.