Private memory table for reduced memory coherence traffic
View Patent ↗A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.
1. A method for memory coherence in a multiple processor system, the method comprising:
responsive to a memory operation from a processing core in a first processing node of the multiple processor system resulting in a cache miss, checking a private region table associated with the processing core, wherein the memory operation attempts to access a memory region stored in memory of a second processing node of the multiple processor system;
responsive to determining the memory region corresponds to an entry in the private region table and the memory region is node-contained in the second processing node, performing the memory operation on the second processing node without snooping the entire multiple processor system, wherein the multiple processor system comprises a plurality of nodes, each node comprises a plurality of chips, each chip comprises a plurality of chiplets, and each chiplet comprises a processing core and a cache associated with the processing core, and wherein the private region table comprises a chiplet-level private region table and a chip-level private region table; and
responsive to the chiplet-level private region table running out of space, moving a selected entry in the chiplet-level private region table to the chip-level private region table and adding a chiplet identifier to the selected entry.
2. The method of claim 1 , further comprising performing the memory operation using snoopy protocol responsive to determining the memory region does not correspond to an entry in the private region table.
3. The method of claim 1 , further comprising performing the memory operation using snoopy protocol responsive to determining the memory region is not node-contained in the second processing node.
4. The method of claim 1 , wherein each entry of the private region table comprises a tag, a size, least recently used (LRU) information, and a count of cache lines stored in a cache of the processing core.
5. The method of claim 1 , wherein a virtual machine executing on the processing core requests memory from a virtual machine manager, the virtual machine manager allocates a remote memory region to the virtual machine, and the virtual machine manager installs an entry in the private region table corresponding to the remote memory region.
6. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
responsive to a memory operation from a processing core in a first processing node of the multiple processor system resulting in a cache miss, check a private region table associated with the processing core, wherein the memory operation attempts to access a memory region stored in memory of a second processing node of the multiple processor system; and
responsive to determining the memory region corresponds to an entry in the private region table and the memory region is node-contained in the second processing node, perform the memory operation on the second processing node without snooping the entire multiple processor system, wherein the multiple processor system comprises a plurality of nodes, each node comprises a plurality of chips, each chip comprises a plurality of chiplets, and each chiplet comprises a processing core and a cache associated with the processing core, and wherein the private region table comprises a chiplet-level private region table and a chip-level private region table; and
responsive to the chiplet-level private region table running out of space, moving a selected entry in the chiplet-level private region table to the chip-level private region table and adding a chiplet identifier to the selected entry.
7. The computer program product of claim 6 , wherein the computer readable program further causes the computing device to perform the memory operation using snoopy protocol responsive to determining the memory region does not correspond to an entry in the private region table.
8. The computer program product of claim 6 , wherein the computer readable program further causes the computing device to perform the memory operation using snoopy protocol responsive to determining the memory region is not node-contained in the second processing node.
9. The computer program product of claim 6 , wherein each entry of the private region table comprises a tag, a size, least recently used (LRU) information, and a count of cache lines stored in a cache of the processing core.
10. The computer program product of claim 6 , wherein a virtual machine executing on the processing core requests memory from a virtual machine manager, the virtual machine manager allocates a remote memory region to the virtual machine, and the virtual machine manager installs an entry in the private region table corresponding to the remote memory region.
11. An apparatus comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
responsive to a memory operation from a processing core in a first processing node of the multiple processor system resulting in a cache miss, check a private region table associated with the processing core, wherein the memory operation attempts to access a memory region stored in memory of a second processing node of the multiple processor system; and
responsive to determining the memory region corresponds to an entry in the private region table and the memory region is node-contained in the second processing node, perform the memory operation on the second processing node without snooping the entire multiple processor system, wherein the multiple processor system comprises a plurality of nodes, each node comprises a plurality of chips, each chip comprises a plurality of chiplets, and each chiplet comprises a processing core and a cache associated with the processing core, and wherein the private region table comprises a chiplet-level private region table and a chip-level private region table; and
responsive to the chiplet-level private region table running out of space, moving a selected entry in the chiplet-level private region table to the chip-level private region table and adding a chiplet identifier to the selected entry.
12. The apparatus of claim 11 , wherein the instructions further cause the processor to perform the memory operation using snoopy protocol responsive to determining the memory region does not correspond to an entry in the private region table.
13. The apparatus of claim 11 , wherein the instructions further cause the processor to perform the memory operation using snoopy protocol responsive to determining the memory region is not node-contained in the second processing node.