System and device for verifying the integrity of a system from its subcomponents
View Patent ↗A system and device for verifying the integrity of a system from its components, the system comprising a plurality of components each having a physical state, the system and the device comprising a processor that is connected to each of the components, the processor configured to verify systemic integrity by performing verification on some or all specified components. The verification may be individual (1, 1) or threshold (n, 1), and may be interactive or non-interactive.
1. A device for verifying the integrity of a system comprising a plurality of components each having a physical state and a physical unclonable function (‘PUF’) including a PUF input and a PUF output and constructed to generate, in response to the input of a specific challenge, an output value that is characteristic to: i) the PUF, ii) the component's physical state, and iii) the specific challenge; the device comprising a memory, and a processor connected to each of the PUF-containing components and configured to perform threshold verification by computing threshold cryptographic operations over multiple shares each associated with a specific component and a response from that component's PUF and combining those threshold cryptographic operations and checking whether a sufficient set of PUF-containing components represented thereby is valid.
2. The device of claim 1 , wherein the processor is configured to perform zero knowledge proof authentication.
3. The device of claim 2 , wherein the processor is further configured to perform elliptic curve cryptography.
4. The device of claim 1 , wherein the processor is configured to perform interactive verification.
5. The device of claim 1 , wherein the processor is configured to perform non-interactive verification.
6. The device of claim 1 , wherein the processor is configured to perform verification of one or more specified groups of components.
7. The device of claim 6 , wherein the system includes critical components and the processor is configured to perform verification on k critical components through a (k, k) sharing construction.
8. The device of claim 1 , wherein the system includes a total of n critical and non-critical components and the processor is configured to perform verification through a (t, n) sharing construction.
9. A system of components configured to attest integrity of the system to a verifying device, each component having a physical state and comprising:
a)a physical unclonable function (‘PUF’) including a PUF input and a PUF output and constructed to generate, in response to the input of a specific challenge, an output value that is characteristic to i) the PUF, ii) the component's physical state, and iii) the specific challenge; and
b)a processor connected to the PUF and configured to, in response to a verification request from the verifying device, provide an input to the PUF input and receive a response from the PUF output, and compute and convey to the verifying device a share for that PUF-containing component of a joint threshold proof associated with a specified set of PUF-containing components.
10. The device of claim 9 , wherein the joint threshold proof is a zero knowledge proof.
11. The device of claim 10 , wherein the system includes a total of n critical and non-critical components and the zero knowledge proof is based upon a (t, n) sharing construction.
12. The device of claim 10 , wherein the zero knowledge proof is based upon an elliptic curve mathematical framework.
13. The device of claim 10 , wherein the zero knowledge proof is based upon a (k, k) sharing construction.
14. The device of claim 10 , wherein the zero knowledge proof is interactive.
15. The device of claim 10 , wherein the zero knowledge proof is non-interactive.