Blister-free polycrystalline silicon for solar cells
View Patent ↗Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.
1. A method of fabricating a solar cell with differentiated P-type and N-type architectures, the method comprising:
forming a first microcrystalline silicon layer on a first thin dielectric layer formed on a back surface of a substrate, the first microcrystalline silicon layer formed by plasma enhanced chemical vapor deposition (PECVD);
forming a P-type amorphous silicon layer on the first microcrystalline silicon layer by PECVD;
forming an insulating layer on the P-type amorphous silicon layer;
patterning the insulating layer and the P-type amorphous silicon layer to form P-type amorphous silicon regions having an insulating cap thereon with trenches in the substrate separating the P-type amorphous silicon regions;
forming a second thin dielectric layer on exposed sides of the P-type amorphous silicon regions and in the trenches;
forming a second microcrystalline silicon layer on the second thin dielectric layer by PECVD;
forming an N-type amorphous silicon layer on the second microcrystalline silicon layer by PECVD;
annealing the first microcrystalline silicon layer and the P-type amorphous silicon regions to form P-type homogeneous polycrystalline silicon regions and annealing the second microcrystalline silicon layer and the N-type amorphous silicon layer to form an N-type homogeneous polycrystalline silicon layer; and
forming conductive contacts to the P-type homogeneous polycrystalline silicon regions and to the N-type homogeneous polycrystalline silicon layer.
2. The method of claim 1 , wherein forming the first microcrystalline silicon layer by PECVD and the P-type amorphous silicon layer by PECVD comprises forming the first microcrystalline silicon layer and the P-type amorphous silicon layer in a first single pass of a PECVD chamber, and wherein forming the second microcrystalline silicon layer by PECVD and the N-type amorphous silicon layer by PECVD comprises forming the second microcrystalline silicon layer and the N-type amorphous silicon layer in a second single pass of a PECVD chamber.
3. The method of claim 1 , wherein forming the first and second microcrystalline silicon layers comprises depositing microcrystalline silicon by PECVD at a deposition rate approximately in the range of 10-40 nanometers per minute.
4. The method of claim 1 , wherein forming the P-type amorphous silicon layer and the N-type amorphous silicon layer comprises depositing amorphous silicon by PECVD at a deposition rate approximately in the range of 50-400 nanometers per minute.
5. The method of claim 1 , wherein forming the microcrystalline silicon layer comprises forming the microcrystalline silicon layer to a thickness approximately in the range of 2-50 nanometers, and wherein forming the amorphous silicon layer comprises forming the amorphous silicon layer to a thickness approximately in the range of 50-400 nanometers.
6. The method of claim 1 , wherein the annealing is performed by heating at a temperature above approximately 400 degrees Celsius for a duration of approximately 10 minutes.
7. A method of fabricating alternating N-type and P-type emitter regions of a solar cell, the method comprising:
forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate;
forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD);
forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD;
doping first regions of the amorphous silicon layer with P-type dopants, and doping second regions of the amorphous polycrystalline silicon layer with N-type dopants; and
annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer, the homogeneous polycrystalline silicon layer having first regions doped with P-type dopants and second regions doped with N-type dopants; and
forming conductive contacts to the first regions of the homogeneous polycrystalline silicon regions and to the second regions of the homogeneous polycrystalline silicon layer.
8. The method of claim 7 , wherein forming the microcrystalline silicon layer by PECVD and the amorphous silicon layer by PECVD comprises forming the microcrystalline silicon layer and the amorphous silicon layer in a single pass of a PECVD chamber.
9. The method of claim 7 , wherein forming the microcrystalline silicon layer comprises depositing microcrystalline silicon by PECVD at a deposition rate approximately in the range of 10-40 nanometers per minute.
10. The method of claim 7 , wherein forming the amorphous silicon layer comprises depositing amorphous silicon by PECVD at a deposition rate approximately in the range of 50-400 nanometers per minute.