Memory module with embedded access metadata
A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like. Modifications to the embedded access metadata can be made by a control module at the memory module itself, thereby reducing overhead at a processor core. In addition, the control module can be configured to record different access metadata for different memory locations of the memory module.
1. A method comprising:
receiving a first memory access request at a memory module associated with a processor, the first memory access request targeted to a first memory address corresponding to a first location of the memory module; and
in response to the first memory access request, adjusting, at the memory module, first access metadata indicating a pattern of accesses to the first memory address of the memory module, wherein adjusting the first access metadata comprises:
reading a value of the first access metadata from a storage array of the memory module;
selecting, at the memory module, a first adjustment rule of a plurality of adjustment rules for the first access metadata;
executing the first adjustment rule at the memory module to generate an adjusted value for the first access metadata; and
storing the adjusted value at the storage array.
2. The method of claim 1 , further comprising:
prefetching data from the memory module to the processor based on the first access metadata.
3. The method of claim 1 , further comprising:
in response to receiving a second memory access request at the memory module, adjusting, at the memory module, second access metadata indicating a pattern of accesses to a second memory address corresponding to a second location of the memory module, the second location different from the first location.
4. The method of claim 3 , wherein the second access metadata indicates access information of a different type than the first access metadata.
5. The method of claim 3 , wherein adjusting the second access metadata comprises:
reading a value of the second access metadata from the storage array;
selecting, at the memory module, a second adjustment rule from the plurality of adjustment rules for the second access metadata, the second adjustment rule different from the first adjustment rule;
executing the second adjustment rule at the memory module to generate an adjusted value for the second access metadata; and
storing the adjusted value for the second access metadata at the storage array.
6. The method of claim 1 , further comprising:
receiving the first adjustment rule at the memory module from the processor; and
configuring a control module of the memory module to execute the first adjustment rule.
7. The method of claim 1 , wherein the first access metadata includes at least one of: a number of read accesses for the first location, a number of write accesses for the first location, a number of bit flips for the first location, an average read latency for the first location and an average write latency for the first location.
8. The method of claim 1 , wherein the first access metadata includes prefetch data indicating a second memory location that was historically accessed after the first location.
9. A device, comprising:
a memory module including:
a first memory address corresponding to a first memory location to store data to be accessed by a processor;
a first memory location to store first access metadata indicating a pattern of accesses to the first memory address;
a control module to adjust the first access metadata by:
reading a current value of the first access metadata;
identifying a first adjustment rule for the first access metadata;
generating an adjusted value for the first access metadata based on the first adjustment rule; and
storing the adjusted value at the first memory location.
10. The device of claim 9 , further comprising:
a processor coupled to the memory module, the processor to prefetch data from the memory module based on the first access metadata.
11. The device of claim 9 , wherein the memory module further includes:
a second memory address corresponding to a second memory location to store data to be accessed by the processor; and
a second memory location to store second access metadata indicating a pattern of accesses to the second memory location.
12. The device of claim 11 , wherein the second access metadata indicates access information of a different type than the first access metadata.
13. The device of claim 12 , wherein the control module is to adjust the second access metadata by:
reading a current value of the second access metadata;
identifying a second adjustment rule for the first access metadata, the second adjustment rule different from the first adjustment rule;
generating an adjusted value for the second access metadata based on the second adjustment rule; and
storing the adjusted value for the second access metadata at the second memory location.
14. The device of claim 9 , wherein the memory module is to:
receive the first adjustment rule from the processor.