Power management in dual memory platforms

1. A system comprising:

a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM;

a switch, connected to an output of the sensor, to control power to the non-volatile RAM;

a voltage regulator to regulate a voltage of the non-volatile RAM and the volatile RAM;

one or more memory slots to receive the non-volatile RAM and the volatile RAM; and

a processor to receive information from the sensor and control the voltage regulator based on the received information.

2. The system of claim 1 , further comprising a vendor specific interface between the sensor and the voltage regulator to transfer information between the sensor and the voltage regulator.

3. The system of claim 1 , wherein the voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.

4. The system of claim 3 , wherein the plurality of registers includes:

a first set of one or more registers to store power consumption of the non-volatile RAM; and

a second set of one or more registers to store power consumption of the volatile RAM.

5. The system of claim 4 , wherein the processor includes precompiled code (p-code) to access the plurality of registers in the voltage regulator to obtain the power consumption information of one or more of the non-volatile RAM and the volatile RAM.

6. The system of claim 1 , wherein the non-volatile RAM includes one or more non-volatile dual inline memory modules (NVDIMMs), and the volatile RAM includes one or more double data rate (DDR) memory modules.

7. An apparatus comprising:

a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM;

a switch, connected to an output of the sensor, to control power to the non-volatile RAM; and

a voltage regulator to regulate a voltage of the non-volatile RAM and the volatile RAM based on the power consumption.

8. The apparatus of claim 7 , further comprising a vendor specific interface between the sensor and the voltage regulator to transfer information between the sensor and the voltage regulator.

9. The apparatus of claim 7 , wherein the voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.

10. The apparatus of claim 9 , wherein the plurality of registers include:

a first set of one or more registers to store power consumption of the non-volatile RAM; and

a second set of one or more registers to store power consumption of the volatile RAM.

11. The apparatus of claim 7 , wherein the non-volatile RAM includes one or more non-volatile dual inline memory modules (NVDIMMs).

12. The method of claim 7 , wherein the volatile RAM includes one or more double data rate (DDR) memory modules.

13. A method comprising:

monitoring a power consumption of a non-volatile random access memory (RAM) and a volatile RAM; and

controlling a voltage regulator coupled to the non-volatile RAM and the volatile RAM based on the power consumption.

14. The method of claim 13 , further comprising transferring information over a vendor specific interface between a sensor and a voltage regulator.

15. The method of claim 13 , further comprising storing power consumption information of the non-volatile RAM and the volatile RAM in a plurality of registers of a voltage regulator.

16. The method of claim 15 , further comprising:

storing power consumption information of the non-volatile RAM in a first set of one or more registers of the voltage regulator; and

storing power consumption information of the volatile RAM in a second set of one or more registers of the voltage regulator.

17. The method of claim 15 , further comprising using precompiled code (p-code) to access the power consumption information of one or more of the non-volatile RAM and the volatile RAM in the plurality of registers.

18. The method of claim 13 , further comprising:

summing the power consumption of one or more of the non-volatile RAM and the volatile RAM;

determining if the total consumed power exceeds a predetermined threshold; and

throttling down the power if the total consumed power exceeds the predetermined threshold.

19. The method of claim 13 , wherein the non-volatile RAM includes one or more non-volatile dual inline memory modules (NVDIMMs), and the volatile RAM includes one or more double data rate (DDR) memory modules.

20. At least one non-transitory computer readable storage medium, comprising a set of instructions which, when executed by a computing device causes the computing device to:

monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM; and

control power to the non-volatile RAM by regulating a voltage of the non-volatile RAM and the volatile RAM based on the power consumption.

21. The at least one computer readable storage medium of claim 20 , wherein the instructions, when executed, cause the computing device to transfer information over a vendor specific interface between a sensor and a voltage regulator.

22. The at least one computer readable storage medium of claim 20 , wherein the instructions, when executed, cause the computing device to store power consumption information of the non-volatile RAM and the volatile RAM in a plurality of registers of a voltage regulator.

23. The at least one computer readable storage medium of claim 22 , wherein the instructions, when executed, cause the computing device to:

store power consumption information of the non-volatile RAM in a first set of one or more registers of the voltage regulator; and

store power consumption information of the volatile RAM in a second set of one or more registers of the voltage regulator.

24. The at least one computer readable storage medium of claim 20 , wherein the instructions, when executed, cause the computing device to use precompiled code (p-code) to access the power consumption information of one or more of the non-volatile RAM and the volatile RAM in the plurality of registers.