IP Library Granted Patent US 9,780,938
Granted Patent B2
US 9,780,938 · App. 14/751,009 · Granted Oct 3, 2017

Patch download with improved acknowledge mechanism

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Quick Facts
Patent No.
US 9,780,938
App. No.
14/751,009
Granted
Oct 3, 2017
Kind
B2
Abstract

Generally, this disclosure provides systems, devices, methods and computer readable media for patch downloading, from a host to a target, with improved acknowledge (ACK) mechanisms including combinations of out-of-sequence, single and aggregate acknowledge mechanisms. The method may include determining a packet size based on buffer capacity of the host; calculating the total number of packets (P) for transmission based on a size of the patch divided by the packet size; and calculating a packet storage capacity (N) of the target, based on buffer capacity of the target divided by the packet size. The method may also include transmitting the P packets to the target, including a sequence number and a portion of the patch, the transmission segmented into one or more cycles of up to N packets. The method may further include receiving ACKs from the target (asynchronously relative to the packet transmissions), the ACKS associated with the sequence numbers.

Claims (45)

1. A system for downloading a patch from a host to a target, said system comprising:

header generation circuitry to:

determine a packet size based on a buffer capacity of said host;

calculate a total number of packets (P) for transmission over a physical transport between said host and said target, P based on a size of said patch divided by said packet size; and

calculate a packet storage capacity (N) of said target, N based on a capacity of a buffer of said target divided by said packet size;

packet transmit circuitry to transmit said P packets to said target, each of said packets comprising a sequence number and a portion of said patch, said transmission segmented into one or more cycles, said cycles comprising up to N packets; and

acknowledgement (ACK) verification circuitry to receive said ACKs from said target, said ACKs associated with one or more of said packet sequence numbers, said ACKS received asynchronously relative to said packet transmissions.

2. The system of claim 1 , wherein said header generation circuitry is further to transmit a first packet and wait to receive an ACK associated with said first packet, said first packet further comprising said packet size, an ACK algorithm type identifier and a patch checksum.

3. The system of claim 1 , wherein said ACK verification circuitry is further to detect a transmission error associated with one of said P packets based on an error indication included in an ACK associated with said packet or based on a failure to receive an ACK associated with said packet.

4. The system of claim 3 , further comprising retry circuitry to retransmit said packet associated with said transmission error up to a predetermined number of attempts until receiving an ACK indicating transmission success.

5. The system of claim 1 , further comprising algorithm selection circuitry to select download operation in a single ACK mode, wherein said ACK is associated with one of said packet sequence numbers, or an aggregate ACK mode, wherein said ACK is associated with a plurality of said packet sequence numbers.

6. The system of claim 5 , wherein said selection of said download operating mode is based on measurement of download speed of one or more previous patch downloads.

7. The system of claim 1 , further to perform said download of a plurality of said patches from said host to a plurality of components of said target.

8. The system of claim 1 , wherein said packet size is further based on characteristics of said physical transport and is chosen to not exceed a threshold value.

9. The system of claim 1 , wherein said packet transmit circuitry is further to select a data rate for said packet transmission based on a characteristic of said physical transport and a desired error rate.

10. The system of claim 1 , wherein said physical transport is a Universal Asynchronous Receiver/Transmitter (UART), a Serial Peripheral Interface (SPI), a Universal Serial Bus (USB) or an Inter-Integrated Circuit bus (I2C).

11. The system of claim 1 , comprising a first physical transport to transmit said packets and a second physical transport to receive said ACKs.

12. The system of claim 1 , comprising a plurality of physical transports to provide parallel transmission of said packets from said host to said target.

13. The system of claim 1 , wherein said packet transmit circuitry is further to: adjust said packet size based on transmission error rates; and

update N based on said adjusted packet size.

14. The system of claim 1 , wherein said packet transmit circuitry is further to calculate a destination address for each of said packets, said destination address associated with a location within said buffer of said target.

15. A non-transitory computer-readable storage medium having instructions stored thereon which when executed by a processor result in the following operations for downloading a patch from a host to a target, said operations comprising:

determining a packet size based on a buffer capacity of said host;

calculating a total number of packets (P) for transmission over a physical transport between said host and said target, P based on a size of said patch divided by said packet size;

calculating a packet storage capacity (N) of said target, N based on a buffer capacity of said target divided by said packet size;

transmitting said P packets to said target, each of said packets comprising a sequence number and a portion of said patch, said transmission segmented into one or more cycles, said cycles comprising up to N packets; and

receiving acknowledgements (ACKs) from said target, said ACKs associated with one or more of said packet sequence numbers, said ACKS received asynchronously relative to said packet transmissions.

16. The non-transitory computer-readable storage medium of claim 15 , further comprising transmitting a first packet and waiting to receive an ACK associated with said first packet, said first packet further comprising said packet size, an ACK algorithm type identifier and a patch checksum.

17. The non-transitory computer-readable storage medium of claim 15 , further comprising detecting a transmission error associated with one of said P packets based on an error indication included in an ACK associated with said packet or based on a failure to receive an ACK associated with said packet.

18. The non-transitory computer-readable storage medium of claim 17 , further comprising retransmitting said packet associated with said transmission error up to a predetermined number of attempts until receiving an ACK indicating transmission success.

19. The non-transitory computer-readable storage medium of claim 15 , further comprising selecting to operate in a single ACK mode, wherein said ACK is associated with one of said packet sequence numbers, or an aggregate ACK mode, wherein said ACK is associated with a plurality of said packet sequence numbers.

20. The non-transitory computer-readable storage medium of claim 19 , wherein said selection of said operating mode is based on measurement of download speed of one or more previous patch downloads.

21. The non-transitory computer-readable storage medium of claim 15 , further comprising performing said download of a plurality of said patches from said host to a plurality of components of said target.

22. The non-transitory computer-readable storage medium of claim 15 , wherein said packet size is further based on characteristics of said physical transport and is chosen to not exceed a threshold value.

23. The non-transitory computer-readable storage medium of claim 15 , further comprising selecting a data rate for said packet transmission based on a characteristic of said physical transport and a desired error rate.

24. A method for downloading a patch from a host to a target, said method comprising:

determining a packet size based on a buffer capacity of said host;

calculating a total number of packets (P) for transmission over a physical transport between said host and said target, P based on a size of said patch divided by said packet size;

calculating a packet storage capacity (N) of said target, N based on a buffer capacity of said target divided by said packet size;

transmitting said P packets to said target, each of said packets comprising a sequence number and a portion of said patch, said transmission segmented into one or more cycles, said cycles comprising up to N packets; and

receiving acknowledgements (ACKs) from said target, said ACKs associated with one or more of said packet sequence numbers, said ACKS received asynchronously relative to said packet transmissions.

25. The method of claim 24 , further comprising transmitting a first packet and waiting to receive an ACK associated with said first packet, said first packet further comprising said packet size, an ACK algorithm type identifier and a patch checksum.

26. The method of claim 24 , further comprising detecting a transmission error associated with one of said P packets based on an error indication included in an ACK associated with said packet or based on a failure to receive an ACK associated with said packet.

27. The method of claim 26 , further comprising retransmitting said packet associated with said transmission error up to a predetermined number of attempts until receiving an ACK indicating transmission success.

28. The method of claim 24 , further comprising selecting to operate in a single ACK mode, wherein said ACK is associated with one of said packet sequence numbers, or an aggregate ACK mode, wherein said ACK is associated with a plurality of said packet sequence numbers, and wherein said selection of said operating mode is based on measurement of download speed of one or more previous patch downloads.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057363/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057186/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2015
From: ATHALYE, SACHIN V.; OBANAIK, VENKATESH S.; FFOULKES-JONES, GERAINT H.; RANGARAJAN, ANAND; HUSSAIN, JAFER; NATAKALA, BALAJI S.; GAFOOR, ABDUL
To: INTEL IP CORPORATION
Reel/Frame 035959/0698 →