IP Library Patent Application 14751096
Patent Application
App. No. 14/751,096

MULTI-LAYER BARRIER FOR METALLIZATION

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Quick Facts
Patent No.
US None
App. No.
14/751,096
Abstract

A solar cell can include a substrate, a semiconductor region disposed in or above the substrate, and a conductive stack that includes a first conductive region, a multi-layer barrier region, and a second conductive region.

Claims (42)

1 . A solar cell, comprising:

a substrate;

a semiconductor region disposed in or above the substrate; and

a conductive contact disposed on the semiconductor region, the conductive contact comprising:

a first conductive region disposed on the semiconductor region,

a first barrier region disposed on the first conductive region,

a second barrier region disposed on the first barrier region, and

a second conductive region disposed over the second barrier region.

2 . The solar cell of claim 1 , wherein the first barrier region includes a refractory metal.

3 . The solar cell of claim 1 , wherein the first conductive region includes aluminum and the second conductive region includes copper.

4 . The solar cell of claim 1 , wherein the first and second barrier regions each have a thickness of approximately 30 nm or less.

5 . The solar cell of claim 1 , wherein the first barrier region includes molybdenum.

6 . The solar cell of claim 1 , wherein the second barrier region includes a nickel-vanadium alloy.

7 . The solar cell of claim 1 , wherein a thickness of the first barrier region is different than a thickness of the second barrier region.

8 . The solar cell of claim 1 , further comprising a third barrier region disposed on the second barrier region, wherein the second conductive region is disposed on the third barrier region.

9 . The solar cell of claim 1 , wherein the conductive contact is on a back side of the solar cell opposite a sunny side of the solar cell.

10 . The solar cell of claim 1 , further comprising additional metal disposed on the second conductive region.

11 . A solar cell, comprising:

a monocrystalline silicon substrate;

a semiconductor region disposed in or above the monocrystalline silicon substrate; and

a conductive stack comprising:

a first conductive layer disposed on the semiconductor region;

a plurality of diffusion-barrier conductive layers disposed on the first conductive layer; and

a second conductive layer disposed on the plurality of diffusion-barrier conductive layers.

12 . The solar cell of claim 11 , wherein the plurality of diffusion-barrier conductive layers comprises a layer of molybdenum and a layer of nickel-vanadium alloy.

13 . The solar cell of claim 11 , wherein a thickness of a first one of the plurality of diffusion-barrier conductive layers is different than a thickness of a second one of the plurality of diffusion-barrier conductive layers.

14 . The solar cell of claim 11 , wherein a combined thickness of the plurality of diffusion-barrier conductive layers is less than approximately 20 nm.

15 . The solar cell of claim 11 , further comprising plated metal disposed on the conductive stack.

16 . A method of fabricating a solar cell, the method comprising:

forming a first conductive region on a semiconductor region disposed in or above a substrate;

forming a multi-layer barrier region on the first conductive region;

forming a second conductive region over the multi-layer barrier region.

17 . The method of claim 16 , further comprising:

annealing the first conductive region, multi-layer barrier region, and second conductive region at a temperature in a range of less than approximately 450° C.; and

patterning the annealed first conductive region, multi-layer barrier region, and second conductive region.

18 . The method of claim 17 , wherein said patterning includes etching the first conductive region, multi-layer barrier region, and second conductive region with a single etchant.

19 . The method of claim 16 , further comprising:

annealing the first conductive region, multi-layer barrier region, and second conductive region;

applying a patterned plating resist to the annealed first conductive region, multi-layer barrier region, and second conductive region;

plating a metal onto the first conductive region, multi-layer barrier region, and second conductive region to form a plurality of metal contacts; and

etching portions of the first conductive region, multi-layer barrier region, and second conductive region between the plurality of metal contacts.

20 . The method of claim 16 , wherein said forming the multi-layer barrier region comprises forming a first barrier layer to inhibit diffusion to or from the first conductive region that includes aluminum and forming a second barrier layer to inhibit diffusion to or from the second conductive region that includes copper.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2025
From: TOTALENERGIES SE
To: MAXEON SOLAR PTE. LTD.
Reel/Frame 072946/0828 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2015
From: BARKHOUSE, DAVID AARON RANDOLPH; JOHNSON, TODD RICHARDS; LOSCUTOFF, PAUL
To: SUNPOWER CORPORATION
Reel/Frame 036570/0017 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2015
From: WOEHL, ROBERT
To: TOTAL MARKETING SERVICES
Reel/Frame 036570/0376 →