Multi-project wafer with IP protection by reticle mask pattern modification
Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.
1. A device comprising:
a substrate comprising first and second chiplet regions;
a first chiplet in the first chiplet region, the first chiplet pertains to a first intellectual property (IP) owner;
a second chiplet in the second chiplet region, the second chiplet pertains to a second intellectual property (IP) owner; and
a device layer disposed on the first and second chiplets, the device layer is a common device layer of the first and second chiplets, wherein
the device layer on the first chiplet contains a first pattern for the first chiplet, the first pattern is consistent with a first mask pattern on an uncovered multi-project wafer (MPW) reticle, the first mask pattern is in accordance with a design of the first IP owner, and
the device layer on the second chiplet contains a second pattern for the second chiplet, the second pattern is consistent with a second mask pattern on the uncovered MPW reticle, the second mask pattern on the uncovered MPW reticle comprises a second modified mask pattern which is different from a design of the second IP owner, wherein
the first chiplet is an operable chiplet, and
the second chiplet is an inoperable chiplet due to the second modified mask pattern on the uncovered MTW.
2. The device of claim 1 wherein the device is a prototype device used to define a final product.
3. The device of claim 1 wherein the device layer is a final interconnect level of the device.
4. The device of claim 1 wherein the second pattern of the second chiplet includes modified device level data of the second chiplet.
5. The device of claim 4 wherein the modified device level data includes design rules of an original device level data designed by the second IP owner.
6. The device of claim 4 wherein the second pattern of the second chiplet includes modified device level data of a via pad level, a pad level, a passivation layer level or a combination thereof.
7. The device of claim 6 wherein the modified device level data of the via pad level includes no via pattern or no via data.
8. The device of claim 6 wherein the modified device level data of the pad level includes a plurality of dummy via fill pattern.
9. The device of claim 6 wherein the modified device level data of the passivation layer level includes no opening pattern or no data.
10. The device of claim 1 wherein the second pattern includes modified design pattern of a device level of the second chiplet.
11. The device of claim 10 wherein:
the modified design pattern of the device level includes a modified merged pattern;
the modified merged pattern includes a merger of first and second modified design patterns, wherein the first modified design pattern includes a plurality of metal lines separated by spaces or dummy lines, and the second modified design pattern is a modified pattern which is different from an original via pattern of a via level.
12. The device of claim 1 wherein the second chiplet includes a plurality of test pads and test components.
13. The device of claim 12 comprising a plurality of test pad conductors to electrically couple the plurality of test pads to render the test pads of the second chiplet inoperable.
14. The device of claim 12 wherein the plurality of test pads are shorted to render the second chiplet inoperable.
15. The device of claim 14 wherein the plurality of test pads are shorted by a conductive line.
16. A device comprising:
a substrate comprising at least first and second chiplet regions;
a first chiplet in the first chiplet region, the first chiplet pertains to a first intellectual property (IP) owner;
a second chiplet in the second chiplet region, the second chiplet pertains to a second intellectual property (IP) owner; and
a device layer disposed over the first and second chiplet regions, the device layer is a common device layer of the first and second chiplets, wherein
the device layer over the first chiplet region contains a first pattern for the first chiplet, the first pattern is consistent with a first mask pattern on an uncovered multi-project wafer (MPW) reticle, the first mask pattern is in accordance with a design of the first IP owner, and
the device layer on the second chiplet region contains a second pattern for the second chiplet, the second pattern is consistent with a second mask pattern on the uncovered MPW reticle, the second mask pattern on the uncovered MPW reticle comprises a second modified mask pattern which is different from a design of the second IP owner, wherein
the second modified mask pattern comprises design rules in accordance with the design of the second IP owner,
the first chiplet is an operable chiplet, and
the second chiplet is an inoperable chiplet due to the second modified mask pattern on the uncovered MPW reticle.
17. The device of claim 16 wherein the second pattern of the second chiplet includes modified device level data of the second chiplet.
18. The device of claim 17 wherein the second pattern of the second chiplet includes modified device level data of a via pad level, a pad level, a passivation layer level or a combination thereof.
19. The device of claim 16 wherein the second pattern includes a modified merged pattern, the modified merged pattern includes a merger of two or more modified design patterns of the second chiplet.
20. A device comprising:
a substrate comprising first and second chiplet regions;
a first chiplet in the first chiplet region, the first chiplet pertains to a first intellectual property (IP) owner;
a second chiplet in the second chiplet region, the second chiplet pertains to a second intellectual property (IP) owner; and
a device layer disposed over the first and second chiplet regions, the device layer is a common device layer of the first and second chiplets, wherein
the device layer over the first chiplet region contains a first pattern for the first chiplet, the first pattern is consistent with a first mask pattern on an uncovered multi-project wafer (MPW) reticle, the first mask pattern is in accordance with a design of the first IP owner,
the device layer over the second chiplet region contains a second pattern for the second chiplet, the second pattern is consistent with a second mask pattern on the uncovered MPW reticle, the second mask pattern comprises a second modified mask pattern which is different from a design of the second IP owner, and
the second mask pattern comprises design rules in accordance with the design of the second IP owner, wherein the second chiplet includes IP protection due to the second modified mask pattern on the uncovered MPW reticle to reduce disclosure of IP information of the second IP owner.