IP Library Granted Patent US 9,461,212
Granted Patent B2
US 9,461,212 · App. 14/752,413 · Granted Oct 4, 2016

Light emitting diode module for surface mount technology and method of manufacturing the same

Inventors: Jong Hyeon Chae (Ansan-si, KR); Jong Min Jang (Ansan-si, KR); Won Young Roh (Ansan-si, KR); Dae Woong Suh (Ansan-si, KR); Min Woo Kang (Ansan-si, KR); Joon Sub Lee (Ansan-si, KR); Hyun A Kim (Ansan-si, KR); Kyoung Wan Kim (Ansan-si, KR); Chang Yeon Kim (Ansan-si, KR)
Assignee: SEOUL VIOSYS CO., LTD.
H01L33/405H01L33/20H01L33/385H01L33/62H01L33/32H01L33/44H01L2224/16H01L2933/0016
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Quick Facts
Patent No.
US 9,461,212
App. No.
14/752,413
Granted
Oct 4, 2016
Kind
B2
Abstract

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

Claims (45)

1. A light emitting diode (LED) comprising:

a first conductive type semiconductor layer;

an active layer positioned over the first conductive type semiconductor layer;

a second conductive type semiconductor layer positioned over the active layer; and

a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer,

wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and

wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region,

wherein the defect blocking layer comprises at least one insulating layer.

2. The LED of claim 1 , further comprising:

a reflective electrode layer positioned over the second conductive type semiconductor layer so as to form an ohmic contact, and covering at least a part of the defect blocking layer; and

a first metal layer forming an ohmic contact with the first conductive type semiconductor layer through the exposed part of the first conductive semiconductor layer.

3. The LED of claim 1 , wherein the defect blocking layer further comprises an additional region surrounding the second region,

the first region, the second region, and the additional region are arranged to be concentric and have a polygonal shape, and

the ratio of the area of the opening region to the area of the masking region gradually decreases along an outward direction from the center of the polygonal shape.

4. The LED of claim 1 , wherein the masking region and the opening region of the defect blocking layer are embossed or engraved.

5. The LED of claim 1 , wherein the defect blocking layer comprises an insulating layer.

6. The LED of claim 1 , further comprising a plurality of mesas each comprising the active layer and the second conductive type semiconductor layer,

wherein the exposed part of the first conductive type semiconductor layer is located in the peripheral region of the plurality of mesas.

7. The LED of claim 2 , wherein the ratio of the area of the opening region to the area of the masking region in the first region is greater than the ratio of the area of the opening region to the area of the masking region in the second region.

8. The LED of claim 4 , wherein the opening region is formed to expose portions of the second conductive type semiconductor layer through a plurality of openings isolated from each other.

9. The LED of claim 4 , wherein the masking region comprises a plurality of masks isolated from each other.

10. The LED of claim 4 , wherein the masking region and the opening region of the defect blocking layer have a circular pattern or hexagonal pattern.

11. The LED of claim 5 , wherein the defect blocking layer comprises a distributed Bragg reflector.

12. The LED of claim 6 , wherein the defect blocking layer is positioned over each of the mesas,

the first and second regions are arranged in the shape of a concentric rectangle, and

the ratio of the area of the opening region to the area of the masking region in the first region is greater than the ratio of the area of the opening region to the area of the masking region in the second region.

13. The LED of claim 6 , further comprising:

a reflective electrode layer positioned over the second conductive type semiconductor layer so as to form an ohmic contact, and covering at least a part of the defect blocking layer; and

a lower insulating layer covering the side surfaces of the plurality of mesas and a part of the top surfaces of the plurality of mesas,

wherein the lower insulating layer comprises a first opening to expose the first conductive type semiconductor layer and a second opening to partially expose the reflective electrode layer.

14. The LED of claim 7 , wherein the defect blocking layer further comprises a third region surrounding the second region, and

the ratio of the area of the opening region to the area of the masking region in the second region is greater than the ratio of the area of the opening region to the area of the masking region in the third region.

15. The LED of claim 8 , further comprising a reflective electrode layer positioned over the second conductive type semiconductor layer so as to form an ohmic contact, and covering at least a part of the defect blocking layer,

wherein the plurality of openings are covered by the reflective electrode layer, and the reflective electrode layer forms an ohmic contact with the second conductive type semiconductor layer through the plurality of openings.

16. The LED of claim 9 , further comprising a reflective electrode layer positioned over the second conductive type semiconductor layer so as to form an ohmic contact, and covering at least a part of the defect blocking layer,

wherein the plurality of masks are covered by the reflective electrode layer, and the reflective electrode layer forms an ohmic contact with the second conductive type semiconductor layer.

17. The LED of claim 13 , further comprising:

a first metal layer forming an ohmic contact with the first conductive type semiconductor layer through the exposed part of the first conductive type semiconductor layer; and

an upper insulating layer covering a part of the first metal layer, the side surfaces of the plurality of mesas, and a part of the second opening,

wherein the upper insulating layer is disposed to expose the first metal layer through a third opening and to partially expose the reflective electrode layer through a fourth opening.

18. The LED of claim 15 , wherein the defect blocking layer is completely covered by the reflective electrode layer.

19. The LED of claim 15 , wherein a part of the masking region is covered by the reflective electrode layer, and the other part of the masking region covers at least a part of the second conductive type semiconductor layer.

20. The LED of claim 17 , further comprising:

a first pad forming an ohmic contact with the first metal layer through the third opening; and

a second pad forming an ohmic contact with the reflective electrode layer through the fourth opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2016
From: CHAE, JONG HYEON; JANG, JONG MIN; ROH, WON YOUNG; KANG, MIN WOO; LEE, JOON SUB; KIM, HYUN A; KIM, KYOUNG WAN; KIM, CHANG YEON
To: SEOUL VIOSYS CO., LTD.
Reel/Frame 037524/0936 →
Priority Claims (2)
KR 10-2012-0071576 · Jul 2, 2012 · national
KR 10-2014-0079218 · Jun 26, 2014 · national
Continuity (3)
Continuation In Part 14588878 · Jan 2, 2015
Continuation In Part PCTKR2013005557 · Jun 24, 2013
Related Publication 20150295138A1 · Oct 15, 2015