IP Library Granted Patent US 9,954,670
Granted Patent B2
US 9,954,670 · App. 14/753,616 · Granted Apr 24, 2018

Frame bit detector in near field communications

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Quick Facts
Patent No.
US 9,954,670
App. No.
14/753,616
Granted
Apr 24, 2018
Kind
B2
Abstract

Described herein are architectures, platforms and methods for (NFC) frame bit detection. A frame bit detector includes a sample-based bit detector that receives samples which may be data and non-data (noise), identifies data bits at every sample input time, and the likelihoods that the identified data bits are part of data. The frame detector includes a maximum likelihood frame detector configured to receive bits from the sample-based bit detector and the likelihood of each bit that the bit is data, and calculate frame likelihood.

Claims (13)

1. A near field communication (NFC) enabled device, comprising:

an NFC receiver comprising a frame bit detector comprised of:

a sample-based bit detector configured to receive demodulated samples obtained from data and non-data, identify data bits at every sample input time, and the likelihoods that the identified data bits are part of data; and

a maximum likelihood frame detector configured to receive bits from the sample-based bit detector and the likelihood of each bit that the bit is data, and calculate frame likelihood.

2. The NFC enabled device of claim 1 , wherein the sample-based bit detector is configured to output all possible results of all received bits at every sample input time, independent of whether the received bits are data or non-data.

3. The NFC enabled device of claim 1 , wherein the sample-based bit detector is configured to calculate bit likelihood based on bit decision error which is a minimum distance to a point in a constellation of bits.

4. The NFC enabled device of claim 1 , wherein the sample-based bit detector is configured to calculate the value of a bit through a slicer, with an input quantity computed by received samples in a bit duration based on a bit coding scheme.

5. The NFC enabled device of claim 4 , wherein the sample-based bit detector is configured to compute the input quantity to the slicer which is modified from a previous input quantity with current input sample before the signal of frame arrival is not valid.

6. The NFC enabled device of claim 1 , wherein the maximum likelihood frame detector is configured to identify full frame or partial frame at every bit arrival from the sample-based bit detector.

7. The NFC enabled device of claim 1 , wherein the maximum likelihood frame detector is configured to calculate frame likelihood by a moving sum of the bit likelihoods of detected data bits sharing a same bit boundary timing.

8. The NFC enabled device of claim 1 , wherein the maximum likelihood detector is further configured to identify frame arrival based on a number of bit likelihoods larger than an average (AVG) value that is estimated when no communication is conducted or given by other software and hardware modules.

9. The NFC enabled device of claim 1 , wherein the maximum likelihood detector is further configured to feedback a signal of frame arrival to sample-based bit detector after frame arrival is identified.

10. The NFC enabled device of claim 1 , wherein the sample-based bit detector is further configured to use signal of frame arrival to reduce power consumption by detecting a bit at the arrival of the last sample of the bit, wherein the last sample of a bit is identified by the timing of a signal of frame arrival.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057363/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057186/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2015
From: ZHU, JIE
To: INTEL IP CORPORATION
Reel/Frame 036282/0174 →