Usage of early bits in wireless communications

1. A device, comprising:

at least one memory that stores computer-executable instructions; and

at least one processor of one or more processors configured to access the at least one memory, wherein the at least one processor of the one or more processors is configured to execute the computer-executable instructions to:

identify a high efficiency frame in accordance with a high efficiency communication standard, received from a first device, the high efficiency frame including at least in part a legacy signal field and a high efficiency signal field;

determine a length field included in the legacy signal field;

determine one or more bits included in the length field;

determine that the high efficiency signal field has been repeated based at least in part on the one or more bits;

combine the high efficiency signal field and the repeated high efficiency signal field into a combined high efficiency signal field; and

decode the combined high efficiency signal field based at least in part on the one or more bits.

2. The device of claim 1 , further comprising:

a transceiver configured to transmit and receive wireless signals;

an antenna coupled to the transceiver; and

one or more processors in communication with the transceiver.

3. The device of claim 1 , wherein the length field includes a length value.

4. The device of claim 1 , wherein the repeated high efficiency signal field is repeated in at least one of a frequency domain and a time domain.

5. The device of claim 3 , wherein the at least one processor of the one or more processors is further configured to execute the computer-executable instructions to determine a remainder of a division of the length value by 3, wherein the length value is not a factor of 3.

6. The device of claim 5 , wherein the high efficiency signal field is repeated in frequency when the remainder is equal to 2.

7. The device of claim 5 , wherein the high efficiency signal field is not repeated in frequency when the remainder is equal to 1.

8. The device of claim 1 , wherein one or more additional bits are determined from a repeated legacy signal field included in the high efficiency frame.

9. The device of claim 8 , wherein the at least one processor of the one or more processors is further configured to execute the computer-executable instructions to determine a polarity of the repeated legacy signal field to determine the one or more additional bits, wherein the polarity is an orientation in a binary phase shift keying modulation.

10. A non-transitory computer-readable medium storing computer-executable instructions which, when executed by a processor, cause the processor to perform operations comprising:

identifying a high efficiency frame in accordance with a high efficiency communication standard, received from a first device, the high efficiency frame including at least in part a legacy signal field and a high efficiency signal field;

determining a length field included in the legacy signal field;

determining one or more bits included in the length field;

determining that the high efficiency signal field has been repeated based at least in part on the one or more bits;

combining the high efficiency signal field and the repeated high efficiency signal field into a combined high efficiency signal field; and

decoding the combined high efficiency signal field based at least in part on the one or more bits.

11. The non-transitory computer-readable medium of claim 10 , wherein the length field includes a length value.

12. The non-transitory computer-readable medium of claim 11 , wherein the computer-executable instructions cause the processor to further perform operations comprising determining a remainder of a division of the length value by 3, wherein the length value is not a factor of 3.

13. The non-transitory computer-readable medium of claim 12 , wherein one or more additional bits are determined from a repeated legacy signal field included in the high efficiency frame.

14. The non-transitory computer-readable medium of claim 13 , wherein the computer-executable instructions cause the processor to further perform operations comprising determining a polarity of the repeated legacy signal field to determine the one or more additional bits, wherein the polarity is an orientation in a binary phase shift keying modulation.

15. The non-transitory computer-readable medium of claim 10 , wherein the repeated high efficiency signal field is repeated in at least one of a frequency domain and a time domain.