Node card utilizing a same connector to communicate pluralities of signals

1. A method comprising:

communicating a plurality of signals between a substrate having a connector and an outside entity;

receiving power, at one or more nodes connected to the substrate, from one or more first signals communicated over the connector;

communicating with the outside entity using one or more second signals communicated over the connector;

translating, by one or more level shifters, a signal on the connector to a signal applied to the one or more nodes, wherein at least one of the plurality of signals is configured to arbitrate usage of a serial port on a node card by the one or more nodes; and

providing a digital signal to the connector to cause an alternative boot procedure.

2. The method of claim 1 , wherein the alternative boot procedure is provided by connecting the digital signal from the connector to a signal on the one or more nodes.

3. The method of claim 1 , wherein the plurality of signals includes an enable signal that, upon assertion, enables the one or more nodes.

4. The method of claim 1 , further comprising:

receiving, at one or more regulators connected to the substrate, power from one or more third signals communicated over the connector, wherein the plurality of signals includes an enable signal that enables the one or more regulators; and

providing, by the one or more regulators, a regulated voltage to the one or more nodes.

5. The method of claim 1 , further comprising routing one or more communication paths to the connector, wherein:

the one or more communication paths are between the one or more nodes and the outside entity, and

the one or more communication paths are XAUI.

6. The method of claim 1 , further comprising routing one or more communication paths to the connector, wherein:

the one or more communication paths are between the one or more nodes and the outside entity, and

the one or more communication paths are serial gigabit media independent interface (SGMII).

7. The method of claim 1 , wherein each of the one or more nodes is a server comprising a system on a chip (SOC), a memory, and a regulator; and wherein the method further comprises:

routing a set of signals from the SOC to one or more serial advanced technology attachment (SATA) connectors through the connector.

8. The method of claim 1 , wherein each of the one or more nodes is a server comprising a system on a chip (SOC), a memory, and a regulator; and wherein the method further comprises:

communicating, through the connector, a set of direct current (DC) values for one of set-up, control, identification, and information.

9. The method of claim 8 , further comprising routing the set of DC values to a set of general purpose input/output (GPIO) pins on each SOC.

10. The method of claim 1 , further comprising communicating a set of joint test action group (JTAG) signals to the one or more nodes.

11. The method of claim 1 , further comprising communicating, through the connector, at least one serial port signal and one or more universal asynchronous receiver/transmitter (UART) signals to the one or more nodes.

12. A non-transitory computer readable medium having instructions stored thereon that, upon execution by a computing device, cause the computing device to perform operations, wherein the instructions comprise:

instructions to communicate a plurality of signals between a substrate having a connector and an outside entity;

instructions to receive power, at one or more nodes connected to the substrate, from one or more first signals communicated over the connector;

instructions to communicate with the outside entity using one or more second signals communicated over the connector; and

instructions to translate, using one or more level shifters, a signal on the connector to a signal applied to the one or more nodes, wherein at least one of the plurality of signals is configured to arbitrate usage of a serial port on a node card by the one or more nodes; and

wherein each of the one or more nodes is a server comprising a system on a chip (SOC), a memory, and a regulator; and wherein the instructions further comprise:

instructions to communicate, through the connector, an alternative boot signal to the SOC to enable an alternative boot by the SOC.

13. The non-transitory computer readable medium of claim 12 , wherein each of the one or more nodes is a server comprising a system on a chip (SOC), a memory, and a regulator; and wherein the instructions further comprise:

instructions to communicate, through the connector, at least one signal to interrupt the SOC.

14. The non-transitory computer readable medium of claim 12 , wherein each of the one or more nodes is a server comprising a system on a chip (SOC), a memory, and a regulator; and wherein the instructions further comprise:

instructions to communicate, through the connector, a signal from the SOC to communicate with the outside entity.

15. A system comprising:

an outside entity; and

a node card, wherein the node card comprises:

a substrate having a connector configured to communicate a plurality of signals between the substrate and the outside entity;

one or more nodes connected to the substrate configured to receive power from one or more first signals communicated over the connector, wherein the one or more nodes are further configured to communicate with the outside entity with one or more second signals over the connector;

one or more level shifters configured to translate a signal on the connector to a signal applied to the one or more nodes; and

a serial port on the node card, wherein at least one of the plurality of signals is configured to arbitrate usage of a serial port by the one or more nodes;

wherein the connector receives a digital signal to cause an alternative boot procedure.

16. The system of claim 15 , wherein each of the one or more nodes is a server comprising a system on a chip (SOC), a memory, and a regulator.

17. The system of claim 16 , wherein the memory is one of a dynamic random access memory (DRAM) and a dual in-line memory module (DIMM), and wherein the memory is connected to the substrate and electrically connected to the SOC.

18. The system of claim 16 , wherein each server has a clock generator chip.

19. The system of claim 16 , wherein each server has a temperature sensor that is electrically connected to the SOC.

20. The system of claim 16 , wherein each server has a nonvolatile memory electrically connected to the SOC, and wherein the nonvolatile memory is one of a storage card, NAND flash, NOR flash, and serial flash.

21. The system of claim 16 , wherein each SOC has a heat sink.

22. The system of claim 15 , wherein the connector is one of a peripheral component interconnect express (PCIe) x1 connector, a PCIe x2 connector, a PCIe x4 connector, a PCIe x8 connector a PCIe x16 connector, and a PCIe x32 connector.

23. The system of claim 15 , wherein the node card further comprises an ethernet transceiver configured to act as an interconnect between the one or more nodes.