IP Library Granted Patent US 9,704,624
Granted Patent B2
US 9,704,624 · App. 14/754,799 · Granted Jul 11, 2017

Integrated circuit (IC) including semiconductor resistor and resistance compensation circuit and related methods

Inventors: Alberto Pagani (Nova Milanese, IT); Alessandro Motta (Cassano d'Adda, IT)
Assignee: STMICROELECTRONICS S.R.L.
H01C7/10H01L23/34H01L27/0207H01L28/20H01L29/36
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Quick Facts
Patent No.
US 9,704,624
App. No.
14/754,799
Granted
Jul 11, 2017
Kind
B2
Abstract

An integrated circuit (IC) may include a semiconductor substrate, and a semiconductor resistor. The semiconductor resistor may include a well in the semiconductor substrate and having a first conductivity type, a first resistive region in the well having an L-shape and a second conductivity type, and a tuning element associated with the first resistive region. The IC may also include a resistance compensation circuit on the semiconductor substrate. The resistance compensation circuit may be configured to measure an initial resistance of the first resistive region, and generate a voltage at the tuning element to tune an operating resistance of the first resistive region based upon the measured initial resistance.

Claims (52)

1. An integrated circuit (IC) comprising:

a semiconductor substrate;

a semiconductor resistor comprising

a well in said semiconductor substrate and having a first conductivity type,

a first resistive region in said well having a serpentine shape and a second conductivity type,

a second resistive region in said semiconductor substrate, adjacent said well, having the first conductivity type, having an L-shape, and being coupled to said first resistive region,

a tuning element carried within said well and associated with said first resistive region, said tuning element having the first conductivity type, and

a testing element coupled between said first and second resistive regions; and

a resistance compensation circuit on said semiconductor substrate and configured to

measure an initial resistance of said first resistive region and said second resistive region based upon said testing element, and

generate a voltage at said tuning element to tune an operating resistance of said first resistive region based upon the measured initial resistance.

2. The IC of claim 1 wherein said tuning element comprises:

an insulating layer above at least a portion of said second resistive region; and

a conductive layer above said insulating layer.

3. The IC of claim 1 wherein said tuning element comprises:

an insulating layer above at least a portion of said first resistive region; and

a conductive layer above said insulating layer.

4. The IC of claim 1 wherein said tuning element comprises:

a doped region in said well having the first conductivity type and having a higher dopant concentration than said well; and

a contact coupled to said doped region.

5. The IC of claim 1 further comprising a temperature sensor on said semiconductor substrate and coupled to said resistance compensation circuit; and wherein said resistance compensation circuit is configured to generate the voltage at said tuning element based upon said temperature sensor.

6. The IC of claim 1 wherein said resistance compensation circuit comprises a processor and a memory coupled thereto; wherein said memory is configured to store at least one resistance compensation value.

7. An integrated circuit (IC) comprising:

a semiconductor substrate;

a plurality of semiconductor resistors each comprising

a well in said semiconductor substrate and having a first conductivity type,

a first resistive region in said well having a serpentine shape and a second conductivity type,

a second resistive region in said semiconductor substrate, adjacent said well, having the first conductivity type, having an L-shape, and being coupled to said first resistive region, and

a tuning element carried within said well and associated with said first resistive region,

a testing element coupled between said first and second resistive regions; and

a temperature sensor on said semiconductor substrate;

a resistance compensation circuit on said semiconductor substrate and coupled to said temperature sensor, said resistance compensation circuit configured to

measure an initial resistance of each first resistive region and each second resistive region, and

generate a voltage at said tuning element to tune an operating resistance of each first resistive region based upon the measured initial resistance and said temperature sensor.

8. The IC of claim 7 wherein said tuning element comprises:

an insulating layer above at least a portion of said second resistive region; and

a conductive layer above said insulating layer.

9. The IC of claim 7 wherein said tuning element comprises:

an insulating layer above at least a portion of said first resistive region; and

a conductive layer above said insulating layer.

10. The IC of claim 7 wherein said tuning element comprises:

a doped region in said well having the first conductivity type and having a higher dopant concentration than said well; and

a contact coupled to said doped region.

11. The IC of claim 7 wherein said resistance compensation circuit comprises a processor and a memory coupled thereto; wherein said memory is configured to store at least one resistance compensation value.

12. A method of compensating resistance in an integrated circuit (IC), the method comprising:

using a resistance compensation circuit on a semiconductor substrate to

measure an initial resistance of first and second resistive regions of a semiconductor resistor based upon a testing element of the semiconductor resistor, the first resistive region being in a well of the semiconductor resistor, the well having a first conductivity type, the first resistive region having a serpentine shape and a second conductivity type, the second resistive region being in the semiconductor substrate, adjacent the well, having the first conductivity type, having an L-shape, and being coupled to the first resistive region, and the testing element coupled between the first and second resistive regions; and

generate a voltage at a tuning element associated with a first resistive region of a semiconductor resistor and having the first conductivity type to tune an operating resistance of the first resistive region based upon a measured initial resistance.

13. The method of claim 12 wherein the tuning element comprises an insulating layer above at least a portion of the second resistive region, and a conductive layer above the insulating layer.

14. The method of claim 12 wherein the tuning element comprises an insulating layer above at least a portion of the first resistive region, and a conductive layer above the insulating layer.

15. The method of claim 12 wherein the tuning element comprises a doped region in the well having the first conductivity type and having a higher dopant concentration than the well, and a contact coupled to the doped region.

16. The method of claim 12 wherein the voltage is generated at the tuning element based upon a temperature sensor on the semiconductor substrate and coupled to the resistance compensation circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061828/0243 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PAGANI, ALBERTO; MOTTA, ALESSANDRO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 036013/0181 →
Continuity (1)
Related Publication 20170005043A1 · Jan 5, 2017