MOSFET devices with asymmetric structural configurations introducing different electrical characteristics

1. An integrated circuit, comprising:

a semiconductor substrate layer having a first conductivity-type dopant at a first dopant concentration level, the semiconductor substrate layer including a first region and a second region;

a well region in the semiconductor substrate layer having the first conductivity-type dopant at a second dopant concentration level greater than the first dopant concentration level, said well region located in the first region but not the second region;

a first body region in the well region at the first region having a second conductivity-type dopant;

a second body region in the semiconductor substrate layer at the second region also having the second conductivity-type dopant;

a first source region in the first body region laterally offset from the well region by a first channel having a first length;

a second source region in the second body region laterally offset from material of the semiconductor substrate layer by a second channel having a second length greater than the first length; and

a gate region extending over both the first and second channels.

2. The integrated circuit of claim 1 , wherein the second length exceeds the first length by a lateral thickness of the well region.

3. The integrated circuit of claim 1 , further comprising:

a drain metal in contact with the semiconductor substrate layer;

a source metal in contact with the first and second source regions and the first and second body regions; and

a gate metal in contact with the gate region.

4. The integrated circuit of claim 1 , wherein the semiconductor substrate layer is an epitaxial layer.

5. The integrated circuit of claim 1 , wherein the well region, the first and second body regions, and the source regions each have a stripe shape.

6. The integrated circuit of claim 1 , wherein the first body region and first source region are associated with a first transistor, and wherein the second body region and second source region are associated with a second transistor, and wherein the first and second transistors have different electrical characteristics.

7. The integrated circuit of claim 6 , wherein an electrical characteristic which is different is selected from the group consisting of zero temperature coefficient, on resistance, threshold voltage and transconductance.

8. An integrated circuit, comprising:

a semiconductor substrate layer having a first conductivity-type dopant at a first dopant concentration level, the semiconductor substrate layer including a first region and a second region;

a first transistor within the first region having an electrical characteristic with a first value, comprising:

a well region in contact with the semiconductor substrate layer having the first conductivity-type dopant at a second dopant concentration level greater than the first dopant concentration level;

a first body region within and in contact with the well region having a second conductivity-type dopant;

a first source region within and in contact with the first body region, the first source region laterally offset from the well region by a first channel having a first length; and

a first gate region extending over the first channel;

a second transistor within the second region having said electrical characteristic with a second value different from the first value, comprising:

a second body region within and in contact with the semiconductor substrate layer having the second conductivity-type dopant;

a second source region within and in contact with the second body region, the second source region laterally offset from material of the semiconductor substrate layer by a second channel having a second length greater than the first length; and

a second gate region extending over the second channel.

9. The integrated circuit of claim 8 , wherein the second length exceeds the first length by a lateral thickness of the well region.

10. The integrated circuit of claim 8 , further comprising:

a drain metal in contact with the semiconductor substrate layer;

a source metal in contact with the first and second source regions and the first and second body regions; and

a gate metal in contact with the gate region.

11. The integrated circuit of claim 8 , wherein the semiconductor substrate layer is an epitaxial layer.

12. The integrated circuit of claim 8 , wherein each of the well region, the first and second body regions and the source regions has a stripe shape.

13. The integrated circuit of claim 8 , wherein the electrical characteristic is selected from the group consisting of zero temperature coefficient, on resistance, threshold voltage and transconductance.

14. An integrated circuit, comprising:

a semiconductor substrate layer;

a well region in the semiconductor substrate layer;

a first body region of a first transistor contained within the well region;

a second body region of a second transistor contained within the semiconductor substrate layer, said second body region separated from said well region by a portion of the semiconductor substrate;

a first source region of the first transistor contained within the first body region, wherein said first source region is laterally offset from the well region by a first channel having a first length;

a second source region of the second transistor contained within the second body region, wherein said second source region is laterally offset from said portion of the semiconductor substrate layer by a second channel having a second length greater than the first length; and

a common gate electrode for both the first and second transistors that extends over both the first and second channels.

15. The integrated circuit of claim 14 , wherein said semiconductor substrate layer is doped with a first conductivity-type dopant; wherein the well region is doped with the first conductivity-type dopant; and wherein the first and second body regions are doped with a second conductivity-type dopant.

16. The integrated circuit of claim 15 , wherein a dopant concentration in the well region exceeds a dopant concentration of the semiconductor substrate layer.

17. The integrated circuit of claim 14 , wherein said semiconductor substrate layer forms a common drain of the first and second transistors.

18. The integrated circuit of claim 17 , further comprising a common source metal in contact with the first and second source regions.

19. The integrated circuit of claim 14 , wherein the second length exceeds the first length by a lateral thickness of the well region.

20. The integrated circuit of claim 14 , wherein the semiconductor substrate layer is an epitaxial layer.

21. The integrated circuit of claim 14 , wherein the well region, the first and second body regions, and the source regions each have a stripe shape.