Sampling circuitry and sampling method for a plurality of electrodes
View Patent ↗A sampling circuitry for a plurality of electrodes the circuitry comprising a plurality of charge amplifiers and a plurality of modulators, wherein each charge amplifier and each modulator, comprised in the plurality of charge amplifiers and the plurality of modulators, respectively, corresponds to an electrode of the plurality of electrodes, wherein each modulator is capable of generating a residue signal and a rough code corresponding to each sampled electrode of the plurality of electrodes, a multiplexer capable of receiving a plurality of residue signals generated by the plurality of modulators, a residue analog to digital converter capable of receiving a multiplexed residue signal from the multiplexer and outputting a digitized multiplexed residue signal, and a digital summation circuitry capable of receiving the digitized multiplexed residue signal and a plurality of rough codes, comprising each rough code corresponding to each sample electrode, and outputting a plurality of output codes.
1. A sampling circuitry for a plurality of electrodes, comprising:
a plurality of charge amplifiers and a plurality of modulators,
wherein each charge amplifier and each modulator, comprised in said plurality of charge amplifiers and said plurality of modulators, respectively, corresponds to an electrode of said plurality of electrodes,
wherein each modulator is capable of generating a residue signal and a rough code corresponding to each sampled electrode of said plurality of electrodes,
a multiplexer capable of receiving a plurality of residue signals generated by the plurality of modulators,
a residue analog to digital converter capable of receiving a multiplexed residue signal from said multiplexer and outputting a digitized multiplexed residue signal, and
a digital summation circuitry capable of receiving said digitized multiplexed residue signal and a plurality of rough codes, comprising each rough code corresponding to each sample electrode, and outputting a plurality of output codes.
2. The sampling circuitry of claim 1 , wherein each electrode of said plurality of electrodes is processed separately in parallel by said each charge amplifier and said each modulator.
3. The sampling circuitry of claim 1 , wherein said digitized multiplexed residue signal is multiplexed between a plurality of integrators comprised by said plurality of modulators.
4. The sampling circuitry of claim 1 , wherein a plurality of phases of frames corresponding to the different electrodes comprised by said plurality of electrodes are phase shifted to facilitate time multiplexing of the residue signals.
5. The sampling circuitry of claim 4 , wherein said residue signal comprising analog signals.
6. The sampling circuitry of claim 4 , wherein said plurality of modulators when resetting their included integrator become incremental analogue to digital converters, and
wherein said phase shifting occurs at the reset of the plurality of incremental analogue to digital converters.
7. The sampling circuitry of claim 6 , wherein the residue signal is sampled between two modulators or two incremental ADC convertors, and
wherein phases of frames for the different electrodes sharing a common residue ADC must be shifted such that the residue conversions for the different electrodes do not overlap.
8. A method of sampling a plurality of electrodes, comprising:
generating, by a plurality of modulators, a plurality of residue signals and a plurality of rough codes, each residue signal and each rough code corresponding to each sampled electrode of said plurality of electrodes,
receiving, by a multiplexer, the plurality of residue signals generated by the plurality of modulators,
receiving, by a residue analog to digital converter, a multiplexed residue signal from said multiplexer and
outputting a digitized multiplexed residue signal, and
receiving, by digital summation circuitry, said digitized multiplexed residue signal and the plurality of rough codes, and outputting a plurality of output codes.
9. The method of claim 8 , wherein each electrode of said plurality of electrodes is processed separately in parallel by said each charge amplifier and said each modulator.
10. The method of claim 8 , wherein said digitized multiplexed residue signal is multiplexed between a plurality of integrators comprised by said plurality of modulators.
11. The method of claim 8 , wherein a plurality of phases of frames corresponding to the different electrodes comprised by said plurality of electrodes are phase shifted to allow time multiplexing of the residue signals.
12. The method of claim 11 , wherein said residue signal comprising analog signals.
13. The method of claim 11 , wherein said plurality of modulators when resetting their included integrator become incremental analogue to digital converters, and
wherein said phase shifting occurs at the reset of the plurality of incremental analogue to digital converters.
14. The method of claim 8 , wherein the residue signal is sampled between two modulators or two incremental ADC convertors, and
wherein phases of frames for the different electrodes sharing a common residue ADC must be shifted such that the residue conversions for the different electrodes do not overlap.