IP Library Granted Patent US 9,585,243
Granted Patent B1
US 9,585,243 · App. 14/757,470 · Granted Feb 28, 2017

Circuit boards and methods of identification and manufacturing thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,585,243
App. No.
14/757,470
Granted
Feb 28, 2017
Kind
B1
Abstract

Methods of manufacturing circuit boards and circuit boards formed thereby to have a surface that is configured to receive circuitry and a notch of a selectable configuration in a lateral edge along the surface of the circuit board boards, and where the selectable configuration is configured to convey identifying information relating to the circuit boards. Such a circuit board can be produced from a panel containing one or more circuit boards, wherein at least one circuit board has a border adjoined and defined by a partition feature that is configured to enable the circuit board to be physically separated from other portions of the panel. Notches having the same of varying selectable configurations may be formed on the at least one circuit board during the manufacturing of the circuit board.

Claims (37)

1. A circuit board comprising:

a surface configured to receive circuitry;

a first notch of a first selectable configuration formed in a first lateral edge of the surface,

wherein the first selectable configuration is configured to convey identifying information that identifies aspects relating to the circuit board; and

at least a portion of a partition feature intersecting with the first notch.

2. The circuit board according to claim 1 , wherein the first selectable configuration includes at least one of a location along the first lateral edge of the surface, a size, or a shape of the first notch.

3. The circuit board according to claim 2 , further comprising a second notch of a second selectable configuration formed in a second lateral edge of the surface, wherein the second selectable configuration is configured to convey identifying information that identifies the aspects relating to the circuit board.

4. The circuit board according to claim 3 , wherein the second selectable configuration includes at least one of a location along the second lateral edge of the surface, a size, or a shape of the second notch.

5. The circuit board according to claim 4 , wherein the first selectable configuration has at least one of a different size, shape, or location from the second selectable configuration.

6. The circuit board according to claim 3 , further comprising at least one additional notch, wherein each notch of the at least one additional notch has a selectable configuration on a third lateral edge of the surface and each selectable configuration is configured to convey identifying information that identifies aspects relating to the circuit board.

7. The circuit board according to claim 3 , wherein the first edge and second edge are a same edge of the surface.

8. A method of manufacturing a circuit board, the method comprising:

forming a first notch, having a first selectable configuration, on a perimeter of a surface of a first circuit board such that the first notch is located within the surface the first circuit board;

configuring the first selectable configuration to convey identifying information that identifies aspects relating to the first circuit board;

forming a first hole on or near the perimeter of the first circuit board such that the first hole is located within the surface of the first circuit board; and

forming a partition feature in a panel that contains the first circuit board,

wherein the partition feature and the first hole intersect.

9. The method according to claim 8 , wherein forming the first hole further comprises drilling the first hole through the surface of the first circuit board.

10. The method according to claim 8 , wherein forming the partition feature further comprises cutting a slot through the panel along the perimeter of the first circuit board.

11. The method according to claim 8 , wherein forming the first notch further comprises:

separating the first circuit board from the panel along the partition feature so that the perimeter of the separated first circuit board defines a first lateral edge, and the first hole defines the first notch in the first lateral edge.

12. The method according to claim 8 , wherein forming the partition feature further comprises cutting a groove in a surface of the panel along the perimeter of the first circuit board.

13. The method according to claim 8 , further comprising:

providing a second circuit board on the panel, wherein the second circuit board has a second surface with a perimeter, and the perimeters of the first and second circuit boards adjoin the partition feature;

forming a second notch having a second selectable configuration on the perimeter of the second circuit board such that the second notch is located within the second surface of the second circuit board; and

configuring the second selectable configuration to convey identifying information that identifies aspects relating to the second circuit board.

14. The method according to claim 13 , wherein forming the second notch further comprises:

forming a second hole on or near the perimeter of the second circuit board,

wherein the partition feature and the second hole intersect.

15. The method according to claim 13 , further comprising: separating the second circuit board from the panel along the partition feature so that the perimeter of the second circuit board defines a second lateral edge, and the second hole is formed in the second lateral edge.

16. The method according to claim 8 , further comprising forming the partition feature after the first hole is formed.

17. The method according to claim 8 , further comprising forming the partition feature before the first hole is formed.

18. The method according to claim 8 , wherein the partition feature partitions the surface of the first circuit board from a frame portion of the panel the method further comprising separating the first circuit board from the frame portion of the panel at the partition feature.

19. The method according to claim 8 , further comprising:

forming a second notch having a second selectable configuration on the perimeter of the first circuit board such that the second notch is located within the surface of the first circuit board; and

configuring the second selectable configuration to convey identifying information that identifies aspects relating to the first circuit board.

20. The circuit board according to claim 1 , further comprising a plurality of notches including the first notch, the plurality of notches formed in the first lateral edge of the surface and having a plurality of different sizes or shapes, or both, wherein a combination of one or more of the plurality of notches are configured to convey information relating to the circuit board.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2016
From: PARDOE, STEPHEN; ROWE, NIGEL
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 037727/0205 →