Signal processing device, signal processing method, and program
Provided is a signal processing device including: a valid clock width calculation unit configured to calculate a valid clock width corresponding to a bit rate of a valid section in which a transport stream (TS) packet exists; and a TS clock signal generation unit configured to generate, on a basis of the valid clock width calculated by the valid clock width calculation unit, a TS clock signal by combining clocks with different frequency dividing rates.
1. A signal processing method comprising:
performing, using a signal processing device, valid clock width calculation processing of calculating a valid clock width corresponding to a bit rate of a valid section in which a transport stream packet exists; and
performing, using the signal processing device, clock signal generation processing of generating, on a basis of the valid clock width calculated, a clock signal by combining clocks with different frequency dividing rates.
2. A non-transitory computer readable medium stored therein instructions, when executed by the signal processing device, allow the signal processing device to perform the signal processing method of claim 1 .
3. The signal processing method according to claim 1 , wherein the valid section clock width is a shortest time period from an antecedent transition of the transport stream clock signal to a subsequent transition of the transport stream clock signal.
4. The signal processing method according to claim 3 , wherein the antecedent transition is a transition of the transport stream clock signal from a logic level to a different logic level that occurs before the subsequent transition.
5. The signal processing method according to claim 4 , wherein the subsequent transition is a next transition of the transport stream clock signal from the logic level to the different logic level that occurs after the antecedent transition.
6. The signal processing method according to claim 1 , further comprising:
generating a parallel clock signal by combining the clocks with the different frequency dividing rates.
7. The signal processing method according to claim 6 , further comprising:
converting the valid section clock width into the parallel clock signal.
8. The signal processing method according to claim 1 , further comprising:
generating a serial clock signal by combining the clocks with the different frequency dividing rates.
9. The signal processing method according to claim 8 , further comprising:
converting a clock width of the parallel clock signal into the serial clock signal.
10. A signal processing device comprising:
clock width calculation circuitry configured to electronically obtain a valid section clock width that corresponds to a bit rate of a valid section in which a transport stream packet exists; and
clock signal generation circuitry configured to combine clocks with different frequency dividing rates to generate a transport stream clock signal, the clock signal generation circuitry being configured to use the valid section clock width to generate the transport stream clock signal.
11. The signal processing device according to claim 10 ,
wherein the valid section clock width is a shortest time period from an antecedent transition of the transport stream clock signal to a subsequent transition of the transport stream clock signal,
wherein the antecedent transition is a transition of the transport stream clock signal from a logic level to a different logic level that occurs before the subsequent transition, the subsequent transition is a next transition of the transport stream clock signal from the logic level to the different logic level that occurs after the antecedent transition.
12. The signal processing device according to claim 10 , wherein the clock signal generation circuitry includes a parallel clock signal generation circuitry configured to generate a parallel clock signal by combining the clocks with the different frequency dividing rates, the parallel clock signal generation circuitry is configured to use the valid section clock width to generate the parallel clock signal.
13. The signal processing device according to claim 12 , wherein the clock signal generation circuitry includes a serial clock signal generation circuitry configured to generate a serial clock signal by combining the clocks with the different frequency dividing rates, the serial clock signal generation circuitry is configured to use a clock width of the parallel clock signal to generate the serial clock signal.