Structure of multi-mode supported and configurable six-input LUT, and FPGA device
View Patent ↗A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.
1. A structure of a multi-mode supported and configurable six-input look-up table (LUT), wherein the six-input LUT has six signal input ends and two signal output ends; and
the structure of the six-input LUT comprises:
a first five-input LUT, a second five-input LUT, a first multiplexer and a second multiplexer, wherein
the first five-input LUT receives five data signals input by five signal input ends of the six-input LUT, and outputs a first output signal according to the five data signals, wherein the first output signal is output by a first signal output end of the six-input LUT;
the second five-input LUT receives five data signals input by the five signal input ends of the six-input LUT and outputs a second output signal according to the five data signals; and
the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal in a multiplexed manner, wherein the first output signal or the second output signal that is output by the second multiplexer in a multiplexed manner is output by a second signal output end of the six-input LUT.
2. The structure according to claim 1 , wherein the first multiplexer is specifically an alternative multiplexer, comprising a first input end, a second input end and an output end; and
the first input end of the first multiplexer accesses a sixth data signal input by one remaining signal input end other than the five signal input ends, the second input end accesses a preset constant, and the output end of the first multiplexer is connected to a multiplexing signal input end of the second multiplexer.
3. The structure according to claim 2 , wherein when the first multiplexer outputs the preset constant according to the configuration mode, the second multiplexer outputs the second output signal in a multiplexed manner according to the preset constant, wherein the second output signal is output by the second signal output end of the six-input LUT, so that the structure of the six-input LUT implements logical functions of two five-input LUTs.
4. The structure according to claim 3 , wherein when the first multiplexer outputs the preset constant in a multiplexed manner, the one remaining signal input end of the six-input LUT other than the five signal input ends is further used for inputting an addend to an adder connected to the six-input LUT.
5. The structure according to claim 2 , wherein the preset constant is 0.
6. The structure according to claim 2 , wherein when the first multiplexer outputs the sixth data signal according to the configuration mode, the second multiplexer outputs the first output signal or the second output signal in a multiplexed manner according to the sixth data signal, wherein the first output signal or the second output signal is output by the second signal output end of the six-input LUT, so that the structure of the six-input LUT implements a logical function of a six-input LUT.
7. A field-programmable gate array (FPGA) device, comprising the structure of the multi-mode supported and configurable six-input look-up table (LUT) according to claim 1 .
8. The structure according to claim 3 , wherein the preset constant is 0.
9. A field-programmable gate array (FPGA) device, comprising the structure of the multi-mode supported and configurable six-input look-up table (LUT) according to claim 2 .
10. A field-programmable gate array (FPGA) device, comprising the structure of the multi-mode supported and configurable six-input look-up table (LUT) according to claim 3 .
11. A field-programmable gate array (FPGA) device, comprising the structure of the multi-mode supported and configurable six-input look-up table (LUT) according to claim 4 .
12. A field-programmable gate array (FPGA) device, comprising the structure of the multi-mode supported and configurable six-input look-up table (LUT) according to claim 5 .
13. A field-programmable gate array (FPGA) device, comprising the structure of the multi-mode supported and configurable six-input look-up table (LUT) according to claim 6 .
14. A field-programmable gate array (FPGA) device, comprising the structure of the multi-mode supported and configurable six-input look-up table (LUT) according to claim 8 .