Vertical transistor with flashover protection
View Patent ↗Technologies are generally described for increase of spacing between source and drain regions of a vertical high voltage transistor without a significant corresponding increase in the die size. In some examples, active silicon (at drain potential) may be removed at an edge of the die in the scribe grid so that the active silicon is approximately below a surface of the edge termination formed by a region of deep dielectric filled trenches. The recessed drain region at the edge of the die may increase a flashover distance without appreciably increasing the die size. Thus, a distance between the recessed drain region and the surface source region may be increased by a combination of vertical and lateral spacing resulting in a smaller overall die size and smaller parasitic capacitances when operated with substantially the same operating voltage.
1. A semiconductor device, comprising:
a substrate having a top portion and a bottom portion;
a source terminal configured in contact with the top portion of the substrate;
a drain region configured in contact with the bottom portion of the substrate; and
an insulating dielectric layer located in the top portion of the substrate and configured in contact with the source region, wherein the substrate includes a cavity region located substantially between the insulating dielectric layer and the bottom portion of the substrate.
2. The semiconductor device of claim 1 , wherein the insulating dielectric layer is located along edges of the semiconductor device in the top portion of the substrate.
3. The semiconductor device of claim 1 , wherein a lateral length of the insulating dielectric layer is less than a flashover distance associated with a particular operating voltage for the semiconductor device.
4. The semiconductor device of claim 1 , wherein the cavity region of the substrate includes a recessed cavity in the substrate positioned below the source region.
5. The semiconductor device of claim 4 , wherein a height of the recessed cavity is less than a height of the cavity region of the substrate.
6. The semiconductor device of claim 1 , wherein the semiconductor device is a vertical transistor.
7. The semiconductor device of claim 1 , wherein the semiconductor device is one of a vertical power transistor, a vertical radio frequency (RF) power transistor, and a vertical double-diffused metal oxide semiconductor (VDMOS).
8. The semiconductor device of claim 1 , wherein a portion of the substrate surrounding the cavity region is doped at a level such that a concentration of carriers in the portion of the substrate surrounding the cavity region is substantially the same as that of the drain region.
9. A method of fabricating a semiconductor device, the method comprising:
forming a drain region at a bottom portion of a substrate;
forming a vertical spacer gate and a source region in the substrate;
forming an insulating dielectric layer in a top portion of the substrate such that the insulating dielectric layer contacts the source region; and
forming a cavity region located substantially between the insulating dielectric layer and the bottom portion of the substrate.
10. The method of claim 9 , wherein forming the drain region comprises:
growing an epitaxial layer on a surface of the substrate;
reducing at thickness of the substrate; and
forming a conductive contact on a backside of the substrate to form a drain terminal.
11. The method of claim 9 , further comprising:
forming the insulating dielectric layer along edges of the semiconductor device in the top portion of the substrate.
12. The method of claim 9 , further comprising:
reducing a length of the insulating dielectric layer at the cavity region of the substrate.
13. The method of claim 9 , further comprising:
forming an additional recessed cavity in the substrate along an edge of the cavity region, wherein a height of the recessed cavity is less than a height of the cavity region.
14. The method of claim 13 , wherein forming the additional recessed cavity comprises employing one or more of anisotropic etching and isotropic etching.
15. The method of claim 13 , wherein forming the additional recessed cavity further comprises employing as deep reactive ion etching (DRIE) process.
16. A method of fabricating a vertical transistor with flashover protection, the method comprising:
forming a drain region at a bottom portion of a substrate;
forming a source region in a top portion of the substrate;
forming an insulating dielectric layer in the top portion of the substrate near an edge of the vertical transistor such that the insulating dielectric layer is configured to contact the source region; and
forming a cavity region in a portion of the substrate and a portion of the insulating dielectric layer along the edge of the vertical transistor effective to increase at flashover distance for a particular operating voltage without increasing a die size.
17. The method of claim 16 , wherein forming the cavity region comprises leaving the bottom portion of the substrate intact such that an additional vertical distance and an additional lateral distance are added to the flashover distance.
18. The method of claim 16 , wherein forming the cavity region comprises carving a recessed cavity in the substrate underneath the insulating dielectric layer such that an additional vertical distance and two additional lateral distances are added to the flashover distance.
19. A method of fabricating a semiconductor device, the method comprising:
forming a drain region at a bottom portion of a substrate;
forming a gate and a source region in a top portion of the substrate;
forming an insulating dielectric layer in a top portion of the substrate near a first edge of the semiconductor device such that the insulating dielectric layer is configured to contact the source region; and
forming a cavity region in the substrate along the first edge of the semiconductor device such that the bottom portion of the substrate is left intact.
20. The method of claim 19 , further comprising:
forming another insulating dielectric layer in the top portion of the substrate near a second edge of the semiconductor device such that the other insulating dielectric layer is configured to contact the source region, wherein the insulating dielectric layer the other insulating dielectric layer are contiguous.