Converter cell with reduced power losses, high voltage multilevel converter and associated method
View Patent ↗It is presented a converter cell ( 10 a; 10 b ) arranged to be used in a high voltage multilevel converter. The converter cell comprises: an energy storage element ( 16 a; 16 b ) and a plurality of switching elements (S 1 , . . . , S 8 ). The plurality of switching elements comprises at least one thyristor (S 3 ; S 8 ) and a plurality of transistors (S 1 , S 2 , S 4 ; S 5 , S 6 , S 7 ). Each one of the at least one thyristor (S 3 ; S 8 ) is provided in a position for a switching element in the converter cell where, during normal operation of the converter cell, the at least one thyristor is in a continuous conducting state. This reduces the power losses of the converter cell. A corresponding multilevel converter and a method are also presented.
1. A converter cell configured for use in a high voltage multilevel converter, the converter cell comprising a full bridge configuration, wherein the full bridge configuration is formed of:
an energy storage element;
only one thyristor; and
only three transistors;
wherein the thyristor of the converter cell is provided in a position for a switching element in the converter cell where, during normal operation of the converter cell, said thyristor is in a continuous conducting state.
2. The converter cell according to claim 1 , wherein each one of the three transistors is an insulated gate bipolar transistor, IGBT.
3. The converter cell according to claim 1 , wherein the thyristor is arranged to be set in a blocking state when a fault occurs on a DC side of the multilevel converter.
4. The converter cell according to claim 1 , wherein the thyristor is an Integrated gate-commutated Thyristor, IGCT.
5. The converter cell according to claim 4 , wherein each one of the three transistors is an insulated gate bipolar transistor, IGBT.
6. The converter cell according to claim 4 , wherein the thyristor is arranged to be set in a blocking state when a fault occurs on a DC side of the multilevel converter.
7. The converter cell according to claim 1 , wherein normal operation is operation when the converter cell is not in a failure mode.
8. The converter cell according to claim 7 , wherein the thyristor is an Integrated gate-commutated Thyristor, IGCT.
9. The converter cell according to claim 7 , wherein each one of the three transistors is an insulated gate bipolar transistor, IGBT.
10. The converter cell according to claim 7 , wherein the thyristor is arranged to be set in a blocking state when a fault occurs on a DC side of the multilevel converter.
11. The converter cell according to claim 7 , wherein the thyristor is provided in every topological position for a switching element in the converter cell where, during normal operation of the converter cell, the thyristor is in a continuous conducting state.
12. The converter cell according to claim 1 , wherein the thyristor is provided in every topological position for a switching element in the converter cell where, during normal operation of the converter cell, the thyristor is in a continuous conducting state.
13. The converter cell according to claim 12 , wherein the thyristor is an Integrated gate-commutated Thyristor, IGCT.
14. The converter cell according to claim 12 , wherein each one of the three transistors is an insulated gate bipolar transistor, IGBT.
15. The converter cell according to claim 12 , wherein the thyristor is arranged to be set in a blocking state when a fault occurs on a DC side of the multilevel converter.
16. A high voltage multilevel converter comprising a plurality of the converter cells according to claim 1 .
17. A method for controlling a converter cell of a high voltage multilevel converter, the converter cell comprising a full bridge configuration, wherein the full bridge configuration is formed of: an energy storage element; only one thyristor; and only three transistors; wherein the thyristor is provided in a topological position for a switching element in the converter cell where, during normal operation of the converter cell, the thyristor is in a continuous conducting state, the method comprising the step of:
setting the thyristor, in a blocking state when a fault occurs on a DC side of the multilevel converter.
18. The method according to claim 17 , wherein the step of setting the thyristor in a blocking state is delayed until the current through the thyristor is negligible.
19. The method according to claim 17 , wherein the step of setting the thyristor in a blocking state is delayed until the current through the thyristor passes through a zero value.
20. The method according to claim 17 , further comprising the step, prior to the step of setting the thyristor in a blocking state, of:
detecting a fault in the DC side of the multilevel converter,
wherein the step of setting the thyristor in a blocking state is based on the step of detecting the fault.
21. A converter cell configured for use in a high voltage multilevel converter, the converter cell comprising a full bridge configuration, wherein the full bridge configuration is formed of:
an energy storage element;
only one diode;
only one thyristor; and
only two transistors;
wherein the thyristor of the full bridge configuration is provided in a position for a switching element in the converter cell where, during normal operation of the converter cell, said thyristor is in a continuous conducting state.
22. A method for controlling a converter cell of a high voltage multilevel converter, the converter cell comprising a full bridge configuration, wherein the full bridge configuration is formed of: an energy storage element, only one diode, only one thyristor and only two transistors; wherein the thyristor is provided in a topological position for a switching element in the converter cell where, during normal operation of the converter cell, the thyristor is in a continuous conducting state, the method comprising the step of:
setting the thyristor, in a blocking state when a fault occurs on a DC side of the multilevel converter.