DRAM with SDRAM interface, and hybrid flash memory module
When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.
1. A memory module comprising:
a substrate having a first side and a second side opposing to the first side;
a plurality of external terminals arranged on a surface and a back surface of the substrate on the first side thereof;
a first memory controller;
a high-speed memory; and
a nonvolatile memory;
wherein the first controller and the high-speed memory are arranged opposite to one another across the substrate; and
wherein the nonvolatile memory is arranged closer to the second side than the first memory controller or the high-speed memory.
2. The memory module according to claim 1 , wherein the high-speed memory is arranged right behind the first memory controller.
3. The memory module according to claim 2 , further comprising:
a plurality of terminals on the back surface of the first memory controller; and
a plurality of terminals on the back surface of the high-speed memory;
wherein each of the terminals come to same corresponding position when the first memory controller and the high-speed memory are joined together back to back; and
wherein some of the terminals in the same corresponding positions are assigned same functions.
4. The memory module according to claim 3 , wherein a terminal pitch of the first memory controller is half of the terminal pitch of the high-speed memory.
5. The memory module according to claim 4 , wherein each of the plurality of terminals is a ball.
6. The memory module according to claim 5 , wherein the non-volatile memories are arranged on both surfaces of the substrate.
7. The memory module according to claim 1 ,
wherein a plurality of the first memory controller and a plurality of the non-volatile memories are provided; and
wherein the number of the first memory controllers is same as that of the high-speed memories.
8. The memory module according to claim 7 ,
wherein the number of the high-speed memories and the first memory controllers is nine, respectively.
9. The memory module according to claim 8 , further comprising:
a second memory controller,
wherein a first group including five of the first controllers is arranged along the first side,
wherein a second group including four of the first controllers is arranged along the first side; and
wherein the second memory controller is arranged between the first group and the second group in the first.
10. The memory module according to claim 9 , wherein the nonvolatile memories are arranged on both surfaces of the substrate.
11. A memory module comprising:
a substrate having a first surface and a second surface opposing to the first surface;
an external connection terminal located at one edge of the substrate and arranged on the first surface and the second surface of the substrate;
a plurality of first memory controllers arranged on the first surface of the substrate;
a plurality of high-speed memories arranged on the second surface of the substrate; and
a plurality of non-volatile memories;
wherein the nonvolatile memories are arranged farther from the terminal than the first memory controllers or the high-speed memories.
12. The memory module according to claim 11 , wherein the high-speed memories are arranged right behind the first memory controllers.
13. The memory module according to claim 12 , further comprising:
a plurality of terminals on the back surface of the first memory controllers; and
a plurality of terminals on the back surface of the high-speed memories;
wherein each of the terminals come to the same corresponding position when the first memory controllers and the high-speed memories are joined together back to back; and
wherein some of the terminals in the same corresponding positions are assigned the same functions.
14. The memory module according to claim 13 , wherein the terminal pitch of the first memory controllers is half of the terminal pitch of the highs-speed memories.
15. The memory module according to claim 14 , wherein the nonvolatile memories are arranged on both surfaces of the substrate.