Semiconductor device
View Patent ↗In order to provide a semiconductor device having a high ESD tolerance, a source wiring ( 32 a ) is formed on a gate ( 31 ) and a source ( 32 ) in a region of an NMOS transistor ( 30 ). The source wiring ( 32 a ) electrically connects the gate ( 31 ), the source ( 32 ), and a ground terminal. A drain wiring ( 33 a ) is formed on a drain ( 33 ) in the region of the NMOS transistor ( 30 ) . The drain wiring ( 33 a ) electrically connects the drain ( 33 ) and a pad ( 20 ) serving as an external connection electrode. Moreover, in the region of the NMOS transistor ( 30 ), the drain wiring ( 33 a ) has the same wiring width as the source wiring ( 32 a ).
1. A semiconductor device, comprising:
a multi-finger NMOS transistor formed by combining fingers having a same shape, the multi-finger NMOS transistor comprising:
a plurality of source regions and a plurality of drain regions alternately arranged on a surface of a semiconductor substrate;
a plurality of channel regions each arranged between one of the plurality of source regions and one of the plurality of drain regions; and
a gate electrode formed above each of the plurality of channel regions;
a source wiring formed on the gate electrode and the plurality of source regions in a region of the multi-finger NMOS transistor, for electrically connecting the gate electrode, the plurality of source regions, and a ground terminal; and
a drain wiring formed on the plurality of drain regions in the region of the multi-finger NMOS transistor, for electrically connecting the plurality of drain regions and a pad serving as an external connection electrode,
each of the fingers of the multi-finger NMOS transistor having a same resistance value when equally-divided in a channel width direction.
2. A semiconductor device according to claim 1 , wherein the source wiring and the drain wiring have a same width in each of the fingers.